RTL processor synthesis for architecture exploration and implementation

Schliebusch, Oliver; Chattopadhyay, Anupam; Leupers, Rainer; Ascheid, Gerd; Meyr, H.; Steinert, M.; Braun, Gunnar; Nohl, Achim

doi:10.1109/date.2004.1269223

Cited by 28 publications

(19 citation statements)

References 14 publications

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“…Thus, they are prone to aforesaid "programming" and "algorithmic" bugs. [3] has integrated assertion-based verification with [15]. However, to the best of our knowledge, no existing high-level framework has an integrated automatic compositional model checking capability.…”

Section: Related Workmentioning

confidence: 99%

“…Existing high-level design frameworks (e.g., [11][13] [15]) provides correct-by-construction property, but do not have integrated formal verification to ensure the correctness of the output implementation that it generates. Thus, they are prone to aforesaid "programming" and "algorithmic" bugs.…”

Section: Related Workmentioning

confidence: 99%

“…The need to apply a high-degree of customization within a short time-to-market makes it intractable to develop application-specific processors (ASIPs) manually. To address this, prior works (e.g., [11][13] [15]) have presented design frameworks that can be used to automatically synthesize custom pipelined processor implementations (usually at the register transfer level) from a precise high-level specification. These frameworks drastically shorten the time to arrive at an implementation.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Integrating formal verification and high-level processor pipeline synthesis

Nurvitadhi

Hoe

Kam

et al. 2011

2011 IEEE 9th Symposium on Application Specific Processors (SASP)

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-When a processor implementation is synthesized from a specification using an automatic framework, this implementation still should be verified against its specification to ensure the automatic framework introduced no error. This paper presents our effort in integrating fully automated formal verification with a high-level processor pipeline synthesis framework. As an integral part of the pipeline synthesis, our framework also emits SMV models for checking the functional equivalence between the output pipelined processor implementation and its input non-pipelined specification. Well known compositional model checking techniques are automatically applied to curtail state explosion during model checking. The paper reports case studies of applying this integrated framework to synthesize and formally verify pipelined RISC and CISC processors.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Integrating formal verification and high-level processor pipeline synthesis

Nurvitadhi

Hoe

Kam

et al. 2011

2011 IEEE 9th Symposium on Application Specific Processors (SASP)

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“…The synthesisable HDL generation approach based on the LISA language [53] produces an HDL model of the architecture. The designer has the choice to generate a VHDL, Verilog or SystemC representation of the target architecture [54].…”

Section: Generation Of Hardware Implementationmentioning

confidence: 99%

Processor Description Languages

Mishra¹,

Dutt²

2008

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Embedded systems present a tremendous opportunity to customise designs by exploiting the application behaviour. Shrinking time-to-market, coupled with short product lifetimes, create a critical need for rapid exploration and evaluation of candidate architectures. Architecture description languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design constraints such as area, power and performance. The ADL is used to specify programmable embedded systems, including processor, coprocessor and memory architectures. The ADL specification is used to generate a variety of software tools and models facilitating exploration and validation of candidate architectures. The paper surveys the existing ADLs in terms of (a) the inherent features of the languages and (b) the methodologies they support to enable simulation, compilation, synthesis, test generation and validation of programmable embedded systems. It concludes with a discussion of the relative merits and demerits of the existing ADLs and expected features of future ADLs.

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“…There is no information available about supporting several HDL backends. The novel RTL processor synthesis framework and the IR are based on our previous work in this area, which is published in [18] and [19]. AN INTERMEDIATE REPRESENTATION The proposed synthesis framework is depicted in figure 1.…”

Section: Related Workmentioning

confidence: 99%

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

Schliebusch¹,

Chattopadhyay²,

Kammler³

et al.

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

Self Cite

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Abstract-Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design space exploration is well supported by numerous tools providing high flexibility and quality, the methodology of automated implementation is limited to simple transformations. Assuming fixed architectural templates, information given in the ADL is directly mapped to a hardware description on Register Transfer Level (RTL). Gate-Level synthesis tools are not able to perform potential optimizations, as the computational complexity grows exponential with the size of the architecture. Information such as exclusiveness, parallelism or boolean relations are spread over multiple modules and therefore hard to determine. In this paper, we present an ASIP synthesis approach from architecture description languages, based on an Intermediate Representation (IR). The IR is the key technology to provide new languageindependent high-level optimizations and to realize different hardware description language backends. The feasibility of our approach is proven in a case-study.

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RTL processor synthesis for architecture exploration and implementation

Cited by 28 publications

References 14 publications

Integrating formal verification and high-level processor pipeline synthesis

Integrating formal verification and high-level processor pipeline synthesis

Processor Description Languages

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

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