RTOS-aware refinement for TLM2.0-based HW/SW designs

Becker, Markus; Guglielmo, Giuseppe Di; Fummi, Franco; Mueller, Wolfgang; Pravadelli, Graziano; Xie, Tao

doi:10.1109/date.2010.5456965

Cited by 11 publications

(9 citation statements)

References 22 publications

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“…In [3] we additionally proposed a four level RTOS and communication refinement flow for TLM2.0-based designs comprising our SystemC RTOS model and the QEMU system emulator for ISS cosimulation. There are some other existing approaches using QEMU dynamic binary translation for ISS.…”

Section: Related Workmentioning

confidence: 99%

A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement

Becker

Zabel

Mueller

2010

Distributed, Parallel and Biologically Inspired Systems

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Section: Related Workmentioning

confidence: 99%

A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement

Becker

Zabel

Mueller

2010

Distributed, Parallel and Biologically Inspired Systems

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“…The simulation speed of these platforms is a key point to allow concurrent hardware and software design. One good candidate for fast simulation of instruction sets is the dynamic binary translation approach, that has been recently advocated by several works [5], [6]. However, although binary translation is well suited for the scalar code, it generally ends up as a host function call to an instruction interpretation function for the SIMD instructions in retargetable solutions.…”

Section: Introductionmentioning

confidence: 99%

Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation

Michel

Fournel

Pétrot

2011

2011 Design, Automation &Amp; Test in Europe

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This paper presents a strategy to speed-up the simulation of processors having SIMD extensions using dynamic binary translation. The idea is simple: benefit from the SIMD instructions of the host processor that is running the simulation. The realization is unfortunately not easy, as the nature of all but the simplest SIMD instructions is very different from a manufacturer to an other. To solve this issue, we propose an approach based on a simple 3-addresses intermediate SIMD instruction set on which and from which mapping most existing instructions at translation time is easy. To still support complex instructions, we use a form of threaded code. We detail our generic solution and demonstrate its applicability and effectiveness using a parametrized synthetic benchmark making use of the ARMv7 NEON extensions executed on a Pentium with MMX/SSE extensions.

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“…In the third step, aRTOS system calls for abstract RTOS simulation are introduced [35], which are replaced by system calls of the target (RT)OS in the final step. [2] In this paper, we first introduce the basic principles of QEMU and abstract RTOS simulation. Thereafter, based on the work in [2], we extend the previous approach and show how the transition from the abstract to the target RTOS can be smoothened even further before we discuss the specification and verification of real-time properties.…”

Section: Introductionmentioning

confidence: 99%

“…However, the approach is limited to the functional evaluation of SW not considering (RT)OS properties. Therefore, it was extended in [2] to a four-level RTOS-aware TLM 2.0-based refinement that starts from functional untimed SystemC PV models. In a first step, the methodology applies SC2OS before models are ported to a canonical abstract RTOS, namely, aRTOS, which is finally replaced by the target (RT)OS running in the full system mode of the QEMU software emulator as given in Fig.…”

Section: Introductionmentioning

confidence: 99%

Verification of real-time properties for Hardware-dependent Software

Mueller¹,

Oliveira²,

Zabel³

et al. 2010

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)

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Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertionbased verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models.

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RTOS-aware refinement for TLM2.0-based HW/SW designs

Cited by 11 publications

References 22 publications

A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement

A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement

Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation

Verification of real-time properties for Hardware-dependent Software

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