Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)
DOI: 10.1109/fpt.2004.1393315
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Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture

Abstract: This paper describes the implementation and evaluation of an algorithm that maps a number of communicating processes to a heterogeneous tiled System on Chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate Quality of Service (QoS). The properties of the algorithm are described and evaluated and a realistic mapping example is given.

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Cited by 39 publications
(32 citation statements)
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“…Methodologies for dynamic run-time reconfiguration of NoCs are presented in [17,22]. Both works assume little or no design time knowledge about the applications and defer mapping decisions to run time.…”
Section: Related Workmentioning
confidence: 99%
“…Methodologies for dynamic run-time reconfiguration of NoCs are presented in [17,22]. Both works assume little or no design time knowledge about the applications and defer mapping decisions to run time.…”
Section: Related Workmentioning
confidence: 99%
“…Therefore, heuristics have to be used to find a solution with a reasonable quality within an acceptable time. In [11], a minimal weight algorithm is proposed to map a digital audio broadcast receiver onto a tiled SoC in a reasonable time, where the optimization metric is to minimize the energy consumption. Run-time mapping offers a number of advantages over design-time mapping, especially for a Cognitive Radio which dynamically changes its behavior.…”
Section: The Design Methodologymentioning
confidence: 99%
“…This spatial mapping of processes is performed at run-time by the spatial mapping tool (SMIT) [4]. OSYRES determines when the spatial mapping tool is called.…”
Section: Introductionmentioning
confidence: 99%