Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Shoa, A.; Shirani, Shahram

doi:10.1007/s11265-005-4841-x

Cited by 27 publications

(17 citation statements)

References 120 publications

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“…The tasks performed by the reconfigurable hardware are usually known as hardware tasks. By dynamically reconfiguring, these systems allow many hardware tasks to be mapped onto the same hardware platform, thus reducing the area and power consumption of the design [4]. In a dynamically reconfigurable system, the sequence of computation and configuration is just determined and handled at run-time.…”

Section: Evolution Of System-on-chipsmentioning

confidence: 99%

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A Survey on Reconfigurable System-on-Chips

Nguyen

Le-Van

Tran

2018

REV J. Electron. Commun.

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Abstract-The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation of multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is the integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

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Section: Evolution Of System-on-chipsmentioning

confidence: 99%

“…dynamic reconfiguration) or compile-time (i.e. static reconfiguration) [4]. Static reconfiguration is the common way for implementing applications with FPGA (Fieldprogrammable Gate Arrays)-like reconfigurable logic fabric.…”

Section: Introductionmentioning

confidence: 99%

A Survey on Reconfigurable System-on-Chips

Nguyen

Le-Van

Tran

2018

REV J. Electron. Commun.

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“…In addition to the previously reviewed work on DPR, there exist two other significant references discussing the advantages and challenges in DPR [117], [118].…”

Section: Dynamic Partial Reconfiguration (Dpr)mentioning

confidence: 99%

“…Shoa and Shirani [117] thoroughly explain different issues in run-time reconfiguration (RTR) systems, and list the implemented systems which support RTR reconfiguration as well as discussing different applications of, and the improvements achieved by applying RTR. An evaluation of DPR for signal and image processing is presented in [118].…”

Section: Dynamic Partial Reconfiguration (Dpr)mentioning

confidence: 99%

Efficient reconfigurable architectures for 3D medical image compression

Ahmad

Amira

2009

2009 International Conference on Field-Programmable Technology

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A AbstractRecently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.

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“…Because of the partial reconfiguration capability in an FPGA, studies have shown that an FPGA-based reconfigurable hardware system can improve performance for many applications [Hauck 1998;Tessier and Burleson 2001;Shoa and Shirani 2005]. For example, Chaubal [2004] successfully implemented a partially reconfigurable network controller onto a Xilinx Virtex XCV1000 FPGA device.…”

Section: Introductionmentioning

confidence: 99%

Temporal floorplanning using the three-dimensional transitive closure subGraph

Yuh

Yang

Chang

2007

ACM Trans. Des. Autom. Electron. Syst.

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Improving logic capacity by time-sharing, dynamically reconfigurable Field Gate Programmable Arrays (FPGAs) are employed to handle designs of high complexity and functionality. In this paper, we use a novel graph-based topological floorplan representation, named 3D-subTCG (3-Dimensional Transitive Closure subGraph), to deal with the 3-dimensional (temporal) floorplanning/placement problem, arising from dynamically reconfigurable FPGAs. The 3D-subTCG uses three transitive closure graphs to model the temporal and spatial relations between modules. We derive the feasibility conditions for the precedence constraints induced by the execution of the dynamically reconfigurable FPGAs. Because the geometric relationship is transparent to the 3D-subTCG and its induced operations (i.e., we can directly detect the relationship between any two tasks from the representation), we can easily detect any violation of the temporal precedence constraints on 3D-subTCG. We also derive important properties of the 3D-subTCG to reduce the solution space and shorten the running time for 3D (temporal) foorplanning/placement. Experimental results show that our 3D-subTCG-based algorithm is very effective and efficient.

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Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Cited by 27 publications

References 120 publications

A Survey on Reconfigurable System-on-Chips

A Survey on Reconfigurable System-on-Chips

Efficient reconfigurable architectures for 3D medical image compression

Temporal floorplanning using the three-dimensional transitive closure subGraph

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