Run-time support for heterogeneous multitasking on reconfigurable SoCs

Marescaux, Théodore; Nollet, V.; Mignolet, J.-Y.; Bartic, Andrei; Moffat, W.; Avasare, Prabhat; Coene, Paul; Verkest, D.; Vernalde, Serge; Lauwereins, Rudy

doi:10.1016/j.vlsi.2004.03.002

Cited by 41 publications

(21 citation statements)

References 15 publications

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“…Marescaux et al [18] report application performance data as a proofof-concept for their packet-switched NoC, but do not offer analysis on the impacts of network design. We use real applications and realistic PE architectures to generate the traffic workloads for our network exploration.…”

Section: Packet-switched Networkmentioning

confidence: 99%

Packet Switched vs. Time Multiplexed FPGA Overlay Networks

Kapre

Mehta

deLorimier

et al. 2006

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

108

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Abstract-Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited degree of PE interconnectivity (e.g. wiring up gates and datapaths). Applications which virtualize PEs may require a large number of distinct PE-to-PE connections (e.g. using one PE to simulate 100s of operators, each requiring input data from thousands of other operators), but with each connection having low throughput compared with the PE's operating cycle time. In these highly interconnected conditions, dedicating spatial interconnect resources for all possible connections is costly and inefficient. Alternatively, we can time share physical network resources by virtualizing interconnect links, either by statically scheduling the sharing of resources prior to runtime or by dynamically negotiating resources at runtime. We explore the tradeoffs (e.g. area, route latency, route quality) between time-multiplexed and packetswitched networks overlayed on top of commodity FPGAs. We demonstrate modular and scalable networks which operate on a Xilinx XC2V6000-4 at 166MHz. For our applications, timemultiplexed, offline scheduling offers up to a 63% performance increase over online, packet-switched scheduling for equivalent topologies. When applying designs to equivalent area, packetswitching is up to 2× faster for small area designs while timemultiplexing is up to 5× faster for larger area designs. When limited to the capacity of a XC2V6000, if all communication is known, time-multiplexed routing outperforms packet-switching; however when the active set of links drops below 40% of the potential links, packet-switched routing can outperform timemultiplexing.

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Section: Packet-switched Networkmentioning

confidence: 99%

Packet Switched vs. Time Multiplexed FPGA Overlay Networks

Kapre

Mehta

deLorimier

et al. 2006

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

108

View full text Add to dashboard Cite

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“…However, the exact nature of the network does not impact the logical computation. The network could use time-multiplexed [23,49] or packet-switched routing [21,51] and could be organized as a mesh (e.g., [6,28] …”

Section: Scalable Networkmentioning

confidence: 99%

“…An alternate approach is to employ a packet-switched network for inter-page routing (e.g., [51]) to avoid the need to compute and configure the network. Packet switches are generally much larger and higher latency than configured switches, but they may be able to handle multirate and dynamic traffic more efficiently.…”

Section: Routingmentioning

confidence: 99%

Stream computations organized for reconfigurable execution

DeHon

Markovsky

Caspi

et al. 2006

Microprocessors and Microsystems

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“…multiprocessors [1], CoRAM [2], sparse graph processing [3], dynamic reconfigurable accelerators [4]). Natively, today's FPGAs provide high dedicated bandwidth with configured interconnect, but only modest dynamically shared bandwidth with hardwired buses [5].…”

Section: Introductionmentioning

confidence: 99%

“…In particular, the larger delays associated with configurable interconnect coupled with the high and predetermined ratio of registers to logic suggests that FPGA NoCs should be pipelined more heavily than ASIC NoCs. A number of recent efforts have shown how to build PS FPGA NoCs [8], [4], [9], but much work remains to develop a systematic understanding of PS NoC design for FPGAs. Two FPGA NoC designs that have begun to depart from the ASIC NoC designs are CONNECT [10] and Split-Merge-based PS NoC [11].…”

Section: Introductionmentioning

confidence: 99%

FPGA optimized packet-switched NoC using split and merge primitives

Huan

DeHon

2012

2012 International Conference on Field-Programmable Technology

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Abstract-Due to their different cost structures, the architecture of switches for an FPGA packet-switched Networkon-a-Chip (NoC) should differ from their ASIC counterparts. The CONNECT network recently demonstrated several ways in which packet-switched FPGA NoCs should differ from ASIC NoCs. However, they also concluded that pipelining was not appropriate for the FPGA switches. We show that the Split-Merge switch architecture is more amenable to pipelining on FPGAs, achieving 300MHz operation-up to three times the frequency and throughput of the CONNECT switches-with only 13-37% more area. Furthermore, we show that the Split-Merge switches are at least as efficient at routing traffic as the CONNECT switches, meaning the 2-3× frequency translates directly into two to three times the application performance.

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Run-time support for heterogeneous multitasking on reconfigurable SoCs

Cited by 41 publications

References 15 publications

Packet Switched vs. Time Multiplexed FPGA Overlay Networks

Packet Switched vs. Time Multiplexed FPGA Overlay Networks

Stream computations organized for reconfigurable execution

FPGA optimized packet-switched NoC using split and merge primitives

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