Stream computations organized for reconfigurable execution

DeHon, André; Markovsky, Yury; Caspi, Eylon; Chu, Michael; Huang, Randy; Perissakis, Stylianos; Pozzi, Laura; Yeh, Joseph; Wawrzynek, John

doi:10.1016/j.micpro.2006.02.009

Cited by 59 publications

(12 citation statements)

References 43 publications

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“…Primitives for FPGAs include sharing FPGA fabric [9,14,26,50,51,93], spatial multiplexing [15,28,84,91], context switch [59,77], memory virtualization [1,18,62,96], relocation [40], preemption [60], and interleaved hardware-software task execution [8,30,84,91]. Core techniques include virtualizing FPGA fabric, including regions [71], tasks [73], processing elements [21], IPC-like communication primitives [66], and abstraction layers/overlays [7,33,48,49,85] Extending OS abstractions to FPGAs is an area of active research. ReconOS [62] extends eCos [22] with hardware threads similar to Hthreads [70].…”

Section: Related Workmentioning

confidence: 99%

“…Previous multi-application FPGA sharing proposals [15,37,92,94] restrict programming models or fail to provide isolation. OS primitives have been combined to form OSes for FP-GAs [31,62,81,82] as well as FPGA hypervisors [21,66,71,73]. Chen et al explore virtualization challenges when FPGAs are a shared resource [14]; AmorphOS [46] provides an OS-level management layer to concurrently share FPGAs among mutually distrustful processes.…”

Section: Related Workmentioning

confidence: 99%

“…21 paper. Code for our various backends can be found at: • AWS F1: https://github.com/JoshuaLandgraf/cascade • SW, DE10-Nano: https://github.com/eschkufz/cascadeA.2 Artifact ChecklistChecklist details: https://ctuning.org/ae/checklist.html• Algorithm: Hardware-accelerated virtualized Verilog runtime • Program: Assorted Verilog programs provided in our repos • Compilation: GCC on Linux, Clang on macOS, AWS FPGA Dev AMI (includes Vivado) for AWS F1, Quartus Lite for DE10-Nano backend • Binary: Our software is compiled from source.…”

mentioning

confidence: 99%

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Compiler-driven FPGA virtualization with SYNERGY

Landgraf

Yang

Lin

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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FPGAs are increasingly common in modern applications, and cloud providers now support on-demand FPGA acceleration in data centers. Applications in data centers run on virtual infrastructure, where consolidation, multi-tenancy, and workload migration enable economies of scale that are fundamental to the provider's business. However, a general strategy for virtualizing FPGAs has yet to emerge. While manufacturers struggle with hardware-based approaches, we propose a compiler/runtime-based solution called Synergy. We show a compiler transformation for Verilog programs that produces code able to yield control to software at sub-clock-tick granularity according to the semantics of the original program. Synergy uses this property to efficiently support core virtualization primitives: suspend and resume, program migration, and spatial/temporal multiplexing, on hardware which is available today. We use Synergy to virtualize FPGA workloads across a cluster of Altera SoCs and Xilinx FPGAs on Amazon F1. The workloads require no modification, run within 3 − 4× of unvirtualized performance, and incur a modest increase in FPGA fabric utilization. CCS CONCEPTS• Hardware → Hardware description languages and compilation; Reconfigurable logic and FPGAs; • Software and its engineering → Compilers; Operating systems.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

mentioning

confidence: 99%

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Compiler-driven FPGA virtualization with SYNERGY

Landgraf

Yang

Lin

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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“…Table 6 shows prior GPU virtualization and trade-offs across virtualization properties (see §2). FPGA virtualization has a long history [31,34,48,57,58,69,74,77,88]. Most prior work relies on hardware-specific features, focuses on sharing in a single protection domain [55], or virtualization primitives [83].…”

Section: Related Workmentioning

confidence: 99%

AvA: Accelerated Virtualization of Accelerators

Peters

Akshintala

et al. 2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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Applications are migrating en masse to the cloud, while accelerators such as GPUs, TPUs, and FPGAs proliferate in the wake of Moore's Law. These trends are in conflict: cloud applications run on virtual platforms, but existing virtualization techniques have not provided production-ready solutions for accelerators. As a result, cloud providers expose accelerators by dedicating physical devices to individual guests. Multi-tenancy and consolidation are lost as a consequence.We present AvA, which addresses limitations of existing virtualization techniques with automated construction of hypervisor-managed virtual accelerator stacks. AvA combines a DSL for describing APIs and sharing policies, deviceagnostic runtime components, and a compiler to generate accelerator-specific components such as guest libraries and API servers. AvA uses Hypervisor Interposed Remote Acceleration (HIRA), a new technique to enable hypervisorenforcement of sharing policies from the specification.We use AvA to virtualize nine accelerators and eleven framework APIs, including six for which no virtualization support has been previously explored. AvA provides nearnative performance and can enforce sharing policies that are not possible with current techniques, with orders of magnitude less developer effort than required for hand-built virtualization support.CCS Concepts • Software and its engineering Virtual machines; Operating systems; Source code generation.

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“…Buffered connections are natural for many streaming systems and have often been used for large-scale concurrent computations (e.g. [26][27][28][29][30][31]). …”

Section: Design Structurementioning

confidence: 99%

Fault-tolerant sub-lithographic design with rollback recovery

Naeimi

DeHon

2008

Nanotechnology

Self Cite

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Shrinking feature sizes and energy levels coupled with high clock rates and decreasing node capacitance lead us into a regime where transient errors in logic cannot be ignored. Consequently, several recent studies have focused on feed-forward spatial redundancy techniques to combat these high transient fault rates. To complement these studies, we analyze fine-grained rollback techniques and show that they can offer lower spatial redundancy factors with no significant impact on system performance for fault rates up to one fault per device per ten million cycles of operation (P f = 10 −7 ) in systems with 10 12 susceptible devices. Further, we concretely demonstrate these claims on nanowire-based programmable logic arrays. Despite expensive rollback buffers and general-purpose, conservative analysis, we show the area overhead factor of our technique is roughly an order of magnitude lower than a gate level feed-forward redundancy scheme.

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Stream computations organized for reconfigurable execution

Cited by 59 publications

References 43 publications

Compiler-driven FPGA virtualization with SYNERGY

Compiler-driven FPGA virtualization with SYNERGY

AvA: Accelerated Virtualization of Accelerators

Fault-tolerant sub-lithographic design with rollback recovery

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