Runtime Partial Reconfiguration for Embedded Vector Processors

Hasan, Muhammad; Ziavras, Sotirios G.

doi:10.1109/itng.2007.170

Cited by 11 publications

(3 citation statements)

References 7 publications

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“…Due to our earlier work on vector processing for embedded applications [7], we focus on such kernels. They are: Autocorrelation between two vectors, RGB to YIQ conversion, and High Pass Grey Filtering (HPG).…”

Section: Methodsmentioning

confidence: 99%

Customized kernel execution on reconfigurable hardware for embedded applications

Hasan

Sotirios

2009

Microprocessors and Microsystems

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To conserve space and power as well as to harness high performance in embedded systems, high utilization of the hardware is required. This can be facilitated through dynamic adaptation of the silicon resources in reconfigurable systems in order to realize various customized kernels as execution proceeds. Fortunately, the encountered reconfiguration overheads can be estimated. Therefore, if the scheduling of timeconsuming kernels considers also the reconfiguration overheads, an overall performance gain can be obtained. We present our policy, experiments, and performance results of customizing and reconfiguring Field-Programmable Gate Arrays (FPGAs) for embedded kernels. Experiments involving EEMBC (EDN Embedded Microprocessor Benchmarking Consortium) and MiBench embedded benchmark kernels show high performance using our main policy, when considering reconfiguration overheads. Our policy reduces the required reconfigurations by more than 50% as compared to brute-force solutions, and performs within 25% of the ideal execution time while conserving 60% of the FPGA resources. Alternative strategies to reduce the reconfiguration overhead are also presented and evaluated.

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Section: Methodsmentioning

confidence: 99%

Customized kernel execution on reconfigurable hardware for embedded applications

Hasan

Sotirios

2009

Microprocessors and Microsystems

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“…There have been significant efforts directed to address this problem within the domain of embedded systems by proposing / utilizing either FRTR or PRTR [Hasan et al 2007;Hymel et al 2007;Hübner and Becker 2006;Jeong et al 1999;Ullmann et al 2004]. On the other hand, many solutions based on hardware caching techniques, virtual memory models, and configuration pre-fetching algorithms have been proposed to utilize PRTR [Li et al 2000;Li and Hauck 2002;Taher 2005;Taher et al 2005] for HPRCs.…”

Section: Introductionmentioning

confidence: 99%

Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing

El-Araby

González

El‐Ghazawi

2009

ACM Trans. Reconfigurable Technol. Syst.

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Runtime Reconfiguration (RTR) has been traditionally utilized as a means for exploiting the flexibility of High-Performance Reconfigurable Computers (HPRCs). However, the RTR feature comes with the cost of high configuration overhead which might negatively impact the overall performance. Currently, modern FPGAs have more advanced mechanisms for reducing the configuration overheads, particularly Partial Runtime Reconfiguration (PRTR). It has been perceived that PRTR on HPRC systems can be the trend for improving the performance. In this work, we will investigate the potential of PRTR on HPRC by formally analyzing the execution model and experimentally verifying our analytical findings by enabling PRTR for the first time, to the best of our knowledge, on one of the current HPRC systems, Cray XD1. Our approach is general and can be applied to any of the available HPRC systems. The paper will conclude with recommendations and conditions, based on our conceptual and experimental work, for the optimal utilization of PRTR as well as possible future usage in HPRC.

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“…This enables the target students to integrate the body of knowledge gained. Specialized hardware components could compensate for the speed of execution and power requirements for an application 2 . Moreover, reconfigurable hardware can ensure reusability of a given chip-area by many embedded applications, thus saving space.…”

Section: Introductionmentioning

confidence: 99%

Course Development In Digital Systems Targeting Reconfigurable Hardware

Hasan¹

2009 Annual Conference &Amp; Exposition Proceedings

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The Netherlands) in 1991 under a Philips postgraduate scholarship program. He subsequently held several faculty positions in an engineering college and in a university in Malaysia. He obtained the Ph.D. in Computer Engineering from New Jersey Institute of Technology. He was awarded the NJIT Hashimoto Fellowship in the academic year 2005-06. He is currently an Assistant Professor of Engineering Technology and Industrial Distribution at TAMU. His research interests include the design and implementation of dynamically reconfigurable computing systems, computer architecture and behavioral synthesis of digital systems.

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Runtime Partial Reconfiguration for Embedded Vector Processors

Cited by 11 publications

References 7 publications

Customized kernel execution on reconfigurable hardware for embedded applications

Customized kernel execution on reconfigurable hardware for embedded applications

Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing

Course Development In Digital Systems Targeting Reconfigurable Hardware

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