Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache

Lee, Seunghan; Kang, Kyungsu; Kyung, Chong-Min

doi:10.1109/tvlsi.2014.2311798

Cited by 12 publications

(13 citation statements)

References 32 publications

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“…Equations (14) to (22) show the power consumption related to the memory system. Equations (14) to (22) show the power consumption related to the memory system.…”

Section: F I G U R E 4 Design Steps Of the 3d Cmpmentioning

confidence: 99%

“…The memory systems and on-chip interconnection network are the main contributors in the power consumption of uncore components. Equations (14) to (22) show the power consumption related to the memory system. In addition, (23) to (29) show the power consumption related to the 3D on-chip interconnection network in the target 3D CMPs in this work.…”

Section: F I G U R E 4 Design Steps Of the 3d Cmpmentioning

confidence: 99%

“…While most of the previous studies on multicore processors have focused on the design of on-chip interconnection networks [12][13][14][15][16][17][18][19] and memory architectures [20][21][22][23][24][25][26][27][28] separately, in this study, to achieve power efficiency, we explore the role of uncore components on CMP performance and power behavior.…”

Section: Introductionmentioning

confidence: 99%

“…For instance, SRAM is a low-density technology that dissipates high leakage power [29,30]; DRAM requires refresh operations to preserve its data integrity. To address these issues, the use of emerging nonvolatile memory (NVM) technologies for on-chip memories have attracted much attention [20][21][22][23][24]29]. To address these issues, the use of emerging nonvolatile memory (NVM) technologies for on-chip memories have attracted much attention [20][21][22][23][24]29].…”

Section: Introductionmentioning

confidence: 99%

“…As the DRAM memory size increases, each refresh operation requires more energy, and more lines need to be refreshed in a given time; therefore, refresh operations become the main source of DRAM power dissipation [31]. To address these issues, the use of emerging nonvolatile memory (NVM) technologies for on-chip memories have attracted much attention [20][21][22][23][24]29]. Many desirable characteristics such as higher density, near zero leakage power, and high resilience against soft errors are some advantages that are offered [25,32].…”

Section: Introductionmentioning

confidence: 99%

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Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

et al. 2018

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Uncore components such as on‐chip memory systems and on‐chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next‐generation analytical models for future chip‐multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex‐optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three‐dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

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“…Equations (14) to (22) show the power consumption related to the memory system. Equations (14) to (22) show the power consumption related to the memory system.…”

Section: F I G U R E 4 Design Steps Of the 3d Cmpmentioning

confidence: 99%

Section: F I G U R E 4 Design Steps Of the 3d Cmpmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

et al. 2018

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References

2017

Three-Dimensional Integrated Circuit Design

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ON–OFF: a reactive routing algorithm for dynamic thermal management in 3D NoCs

Taheri

Mohammadi

Patooghy

2018

IET Computers & Digital Techniques

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Dynamic thermal management (DTM) techniques of three-dimensional (3D) Network-on-Chips (NoCs) are employed to rescue the chip from thermal difficulties. Reactive routing algorithms, which utilise router throttling technique as a popular DTM, disregard distribution of heat generation of routers resulting in more throttled routers as well as long packet delays in throttled processing elements. This study proposes a reactive routing algorithm for 3D NoCs to (i) dynamically detour packets from hot zones containing throttled routers and (ii) minimise the number of required router throttling in the network. The proposed routing algorithm defines two virtual networks to enhance the path diversity for packets in each layer of 3D NoCs. The selection of diverse paths distributes heat generation to alleviate the thermal variance. The proposed routing algorithm is analysed by turn model to achieve deadlock freedom. Access Noxim simulator is also used to evaluate the performance and the thermal behaviour of the proposed routing algorithm in the variety of conditions. Results show that the proposed routing algorithm improves temperature variance by 9-39% and reduces number of throttled routers by 16-86%, which is achieved at the cost of one extra virtual channel per each physical channel in the XY-plane.

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Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache

Cited by 12 publications

References 32 publications

Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

References

ON–OFF: a reactive routing algorithm for dynamic thermal management in 3D NoCs

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