RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC

Elmohr, Mahmoud A.; Eissa, Ahmed S.; Ibrahim, Moamen; Khamis, Mostafa; El-Ashry, Sameh; Shalaby, Ahmed; Abdelsalam, Mohamed; El-Kharashi, M. Watheq

doi:10.1109/pdp2018.2018.00103

Cited by 14 publications

(8 citation statements)

References 12 publications

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“…The 3 rd column classifies works by detailing how the computation is implemented. Noticeably, RISC-V was received considerable attention from research, resulting in the majority of the works, which either adopt RISC-V cores exclusively [2,6,7] or use it in an on-chip heterogeneous fashion [4,8,15]. Another observed aspect is that many-cores are increasingly adopting accelerators to reach energy efficiency in complex applications, specifically to support machine learning [4,12,13,15].…”

Section: Overview Of Many-core Platforms and Debuggingmentioning

confidence: 99%

“…The 4 th column classifies works by their memory organization. Few architectures adopt purely distributed system [6,11,14]. Most systems use a hybrid shared memory system, which includes a private memory (L1 or scratchpad) with a logically shared but physically distributed last level shared memory [1,2,7,12,15].…”

Section: Overview Of Many-core Platforms and Debuggingmentioning

confidence: 99%

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ManyGUI: A Graphical Tool to Accelerate Many-core Debugging Through Communication, Memory, and Energy Profiling

Ruaro

Martin

2022

System Engineering for Constrained Embedded Systems

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The debugging and validation of the many-core design is a complex task due to numerous events happening in the system simultaneously. Current state-of-the-art many-cores are strongly based on waveforms and log files to validate their behavior during simulation. Our hypothesis is that, as happened with ASIC development, a Graphical User Interface (GUI) can significantly accelerate the many-core development. To sustain that, we propose an open-source GUI tool called ManyGUI for many-core debugging. ManyGUI is organized in a framework that collects and classifies high-level events during simulation related to computation (executed CPU instructions), memory, and communication (NoC packets). Such events are shown graphically to the developer through a set of intuitive and practical frames. We evaluate ManyGUI in a silicon-proven state-of-the-art open-source manycore called OpenPiton, which uses RISC-V 64-bits CPU, 3 NoCs, and a distributed/shared cache memory organization. Results show that ManyGUI allows the developer to rapidly obtain a comprehensive view of the many-core behavior in terms of communication statistics (packets paths, link utilization), memory statistics (memory access, miss rate), and energy (CPU, memory, and NoC). CCS CONCEPTS• Hardware → Simulation and emulation; • Computer systems organization → Multicore architectures.

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Section: Overview Of Many-core Platforms and Debuggingmentioning

confidence: 99%

Section: Overview Of Many-core Platforms and Debuggingmentioning

confidence: 99%

ManyGUI: A Graphical Tool to Accelerate Many-core Debugging Through Communication, Memory, and Energy Profiling

Ruaro

Martin

2022

System Engineering for Constrained Embedded Systems

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“…Also, the framework allows the integration of HLS based accelerators to the architecture. RVNoC [13] framework is a design time configurable RISC-V NoC-based MPSoC to integrate many RISC-V cores using a reconfigurable NoC architecture to allow large system scalability in term of computing elements. However, it leaks the flexibility manner of cluster/tile based architectures to host multiple RISC-V PEs or hardware accelerators on a single processing unit with a shared or local memory system which gives a second level of design scalability inside the cluster/tile node.…”

Section: Related Work and Backgroundmentioning

confidence: 99%

“…However, it does not support the tightly coupled integration of HW accelerators directly with PEs like the case of cluster/tile based architectures. Moreover, the generated architectures [13], [14] lacking fine configurations regarding memory types/sizes and processing cores as proposed by our modular architecture. In contrast, Vestias and Neto [15], José et al [16] proposed a configurable FPGA-based manycore overlay for applications acceleration.…”

Section: Related Work and Backgroundmentioning

confidence: 99%

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators

2020

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Multi-/Many-core architectures are emerging as scalable, high-performance and energy-efficient computing platforms suitable for a variety of application domains from edge to cloud computing. Recently, the appearance of RISC-V open-source ISA creates new possibilities to develop customized computing platforms with high savings in the non-recurring engineering costs. Moreover, the current trends toward open-source hardware frameworks are aimed to reduce design time and cost for complex system-on-chip architectures. Therefore, modularity and re-usability of hardware components are major challenges for flexible hardware architectures. The motivation behind this work is to introduce a modular cluster-based many-core architecture for FPGA accelerators that is re-usable and flexible tailored to implement different many-core taxonomies with less design time and costs by using regular and replicated sets of computing, memory, and interconnection blocks. The proposed many-core architecture is built using multiple processing clusters coupled with a NoC for communication which allows a high degree of design scalability. The processing cluster inside features a configurable multi-core architecture consisting of multiple RISC-V processing elements (PE) tightly coupled with a bus-based interconnection for intra-cluster communication using parameterized scratchpad shared memory. Each PE features a single RISC-V core with a tightly coupled parameterized scratchpad local memory and generic AXI interface. Evaluation results demonstrate that the proposed architecture features a scalable computing performance of 501 MOp/s for 4 clusters and 878 MOp/s for 8 clusters. Moreover, a scalable memory bandwidth up to 4.3 GB/s is achieved for 9 clusters with a power consumption of 1.4 W per cluster utilizing 7.7% of on-chip memory resources. The many-core architecture is implemented and evaluated on Xilinx Virtex Ultrascale+ with the feature of changing the architecture configurations during run-time using dynamic and partial reconfiguration which provides more flexibility and re-usability.INDEX TERMS Many-core architecture, parallel computing, RISC-V, network-on-chip (NoC), field programmable gate array (FPGA), reconfigurable computing.

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“…Elmohr et al [8] present an MPSoC framework based on the RISC-V Instruction Set Architecture and a configurable flit-based router for interconnecting cores. The framework enables a set of configurations at the NoC level (topology, buffer size, routing algorithm), with limited information about the software and application environment control.…”

Section: Related Workmentioning

confidence: 99%

Memphis: a framework for heterogeneous many-core SoCs generation and validation

Ruaro

Caimi

Fochi

et al. 2019

Des Autom Embed Syst

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This work presents Memphis, which comprises a flexible EDA framework and a manycore model for heterogeneous SoCs. The framework, together with the many-core model supports the integration of processors, network interfaces, routers, and peripherals. A set of tools enable a decoupled generation and compilation of the hardware, operating systems, and applications. The hardware model is cycle-accurate, with a SystemC model to speed up simulation time and a VHDL model enabling prototyping in FPGAs devices. The framework provides a rich set of graphical debugging tools enabling an easy and intuitive understanding of computation and communication events happening at runtime. The coupled integration of the platform model to the EDA framework makes Memphis well suited to be employed in research and teaching. As case studies, we provide a set of evaluations addressing the many-core generation, simulation, and debugging. Different applications sets were employed, enabling to characterize the computation and communication performance of the many-core, as well as, evaluate an AES encryption application performance according to different levels of parallelism.

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RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC

Cited by 14 publications

References 12 publications

ManyGUI: A Graphical Tool to Accelerate Many-core Debugging Through Communication, Memory, and Energy Profiling

ManyGUI: A Graphical Tool to Accelerate Many-core Debugging Through Communication, Memory, and Energy Profiling

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators

Memphis: a framework for heterogeneous many-core SoCs generation and validation

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