S/sup 2/I: a two-step approach to switched-currents

ACE16k: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs

“…6, is driven by three different pixel values, , and so that the current which flows into the PE is (1) where the operator denotes the convolution product of the template and the pixel value matrix, and is the offset term generated by the one-transistor multipliers. This offset term is eliminated by using a high-accuracy current memory [13], [15]. Fig.…”

“…Fig. 7 shows a conceptual schematic of the PE input block including the S3I current memory used for offset cancellation, based on [15]. The resulting current (2) is either steered to the ACE-BUS, or to the input of a capacitiveinput current comparator [16] whose output is connected to the ACE-BUS through an analog switch.…”

A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O

“…The current conveyor also includes an offset calibration current memory to reduce the input-referred offset voltage of the OTA, which directly appears in the signal path and produces space-variant errors. The offset term generated by the multipliers, plus the biasing current from , are stored, and then drained away from the input current, in an current memory, which is an extension of the approach in [19]. We will not discuss here the needs which motivated selecting such a memorization technique.…”

A switched-current third-order oversampling modulator with coupled differential replica FMC

“…A dummy cell, comprising a dummy switch and a dummy circuit, is adopted to reduce the clock feedthrough (CFT) error [5]. A modified memory cell, which is composed of either the regulator cascode circuit or the S 2 I, has been developed to improve the transmission error [6]. Unfortunately, those modified techniques are complex.…”