2008 10th International Workshop on Signal Processing for Space Communications 2008
DOI: 10.1109/spsc.2008.4686718
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S-UMTS Processor Key Technologies demonstrator

Abstract: The S-UMTS Processor Key Technologies demonstrator (built under ESA contract 16024/02/NL/JA) is a Digital Signal Processor (DSP) prototype demonstrating a number of architectures and technologies relevant to the next generation of mobile missions. An advanced testbed capable of simulating a variety of antenna types has been constructed. Two beamforming techniques are implemented and preliminary test results are presented.

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“…For non rectangular placement of the radiating elements and/or beams, more complex theoretical frameworks must be re-called as those relevant to the Multi-Dimensional FFT (MD-FFT) [30]. Techniques based on MD-FFTs for planar lattices are particularly well suited for periodic arrays and have been implemented, tested and validated in a real-time proof-ofconcept demonstrator [38] for arrays with number of beams to be generated equal to the number of antenna elements. In the present case, the high overlapping of the beams requires an oversizing of the MD-FFT and FFT input pruning, zero padding or Reconfigurable-MD-FFT architectures [42] can offer further advantages in terms of complexity reduction when there is a large unbalance in the numbers N B , N F B , N F T and N T .…”
Section: A Pragmatic M-mimo Payload Designmentioning
confidence: 99%
“…For non rectangular placement of the radiating elements and/or beams, more complex theoretical frameworks must be re-called as those relevant to the Multi-Dimensional FFT (MD-FFT) [30]. Techniques based on MD-FFTs for planar lattices are particularly well suited for periodic arrays and have been implemented, tested and validated in a real-time proof-ofconcept demonstrator [38] for arrays with number of beams to be generated equal to the number of antenna elements. In the present case, the high overlapping of the beams requires an oversizing of the MD-FFT and FFT input pruning, zero padding or Reconfigurable-MD-FFT architectures [42] can offer further advantages in terms of complexity reduction when there is a large unbalance in the numbers N B , N F B , N F T and N T .…”
Section: A Pragmatic M-mimo Payload Designmentioning
confidence: 99%
“…DBF techniques based on Fast-Fourier-Transforms (FFTs) on planar lattices 11 are particularly well suited for periodic active arrays and have been recently implemented, tested and validated in real-time proof-of-concept demonstrators 12 (Figure 7 reports some test results). …”
Section: Analog and Digital Butler Matricesmentioning
confidence: 99%