SAMURAI: An accurate method for modelling and simulating non-stationary Random Telegraph Noise in SRAMs

Accurate Prediction of Random Telegraph Noise Effects in SRAMs and DRAMs

“…These simulations can be performed by any SPICE simulator, without modifying the simulator. Our paper [16] illustrates these steps in detail, using a 90 nm SRAM cell and SpiceOPUS [25] as the simulator.…”

“…Thus, MUSTARD and SAMURAI each have their own strengths, and together they overcome the challenges associated with circuit-level RTN analysis. 3) We validate SAMURAI against analytical expressions known for stationary RTN (Section V), by showing that the statistical properties of SAMURAI-generated RTN 3 SAMURAI stands for SRAM analysis via Markov uniformization with RTN awareness incorporated, and was presented [16] at DATE 2011. This paper elaborates on [16], providing additional results and comparisons against a previously published method [15].…”

Compact modeling and simulation of Random Telegraph Noise under non-stationary conditions in the presence of random dopants

“…Previous work by [9,10] did not either account for the impact of RDF on noise produced by a trap, or detail the trap energy distribution and track the difference of quasi-Fermi level and the trap energy level (E F À E Ti ) ''on the fly''. A U-shape distribution is crucial for explaining relevant behavior under non-stationary excitation, as for instance noise reduction under forward body biasing, as discussed below.…”

“…While the RTN effects have been discussed in length by various authors [2][3][4][5][6], both in conjecture with and without RDF, only few discuss them from a circuit application perspective [9][10][11]. None of them present a framework for circuit level simulation considering the RTN source and the circuit as a coupled system, considering the interplay between RTN sources and circuit bias points, and tracking simultaneously the evolution of both RTN and circuit bias points.…”

Statistical analysis of random telegraph noise in digital circuits

“…On the other hand, many existing researches used timeconsuming SPICE simulation to obtain the transient response under RTN [14]- [18]. This method can be used for predicting read/write failures in memories, but it is useless for evaluating the timing of CMOS logic circuits.…”