SAP-a program package for three-dimensional interconnect simulation

Sabelka, R.; Selberherr, S.

doi:10.1109/iitc.1998.704913

Cited by 6 publications

(4 citation statements)

References 5 publications

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“…An advantage of this gridding procedure is its simplicity and robustness. The three-dimensional gridded structure is then input to SCAP [2] to extract the capacitor values. It uses the energy method for high numerical accuracy and the solver is based on optimized finite-element techniques.…”

Section: Simulation Methodsmentioning

confidence: 99%

“…Due to the nature of this data format there are problems in the linkage with the finite element based capacitance and resistance/thermal simulators that require a tetrahedral grid. The preprocessor laygrid [2] was written to generate three-dimensional (tetrahedral) grids compatible with the used finite-element simulators. The structures are formed and gridded by stacking planar layers (that are associated with some thickness).…”

Section: Simulation Methodsmentioning

confidence: 99%

“…Realistic solid modeling of these cells requires also accurate topography simulators. We present an integrated environment where all steps towards maximum precision are considered, namely the use of accurate topograph} simulation [1] (with optional lithography analysis) and a state of the art finite-element solver [2] (see Fig. 1).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Rigorous Capacitance Simulation of DRAM Cells

Martins¹,

Sabelka²,

Pyka³

et al. 1998

Simulation of Semiconductor Processes and Devices 1998

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As dynamic RAM cell size is being scaled down, the storage capacitor design becomes more difficult because its capacitance cannot scale as much. The solutions are leading to complex structures which require an accurate description of the fabrication process, making technology CAD (TCAD) simulations necessary. We introduce a set of layout-driven TCAD tools to perform capacitance extraction of three-dimensional structures created by rigorous topographic simulation, suitable in the development of new cell configurations. Simulation results are also given and compared with measured data.

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Section: Simulation Methodsmentioning

confidence: 99%

Section: Simulation Methodsmentioning

confidence: 99%

See 1 more Smart Citation

Rigorous Capacitance Simulation of DRAM Cells

Martins¹,

Sabelka²,

Pyka³

et al. 1998

Simulation of Semiconductor Processes and Devices 1998

Self Cite

View full text Add to dashboard Cite

show abstract

“…The model describes the proximity effect and the skin effect typically arising at higher frequencies as well. The three-dimensional FEM simulation software SAP (Smart Analysis Programs) [7] is extended to implement the developed model. Simulation results demonstrate the physical plausibility of the applied model and numerical methods, as well as the necessity of three-dimensional simulations.…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional on-chip inductance and resistance extraction

Nentchev

Selberherr

2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

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An efficient three-dimensional finite element frequency domain method to extract the inductance and resistance of small structures like on-chip interconnects or on-chip inductors is presented. Skin effect and proximity effect are taken into account. The parameters are obtained from the field energy calculated from the magnetic field distribution in the simulation domain. The small dimensions of the domain of interest provide the opportunity of using the optimized model of dominant magnetic field even at very high operating frequencies. Vector and scalar shape functions are used for finite element equation system assembling. Series of simulations for an instancing on-chip inductor at frequencies between 1 MHz and 100 GHz are performed to extract the parameters and to visualize the field distributions in the simulation area.

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Precise chip and package 3D capacitance simulations of realistic interconnects using a general purpose FEM-tool

Hieke¹

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)

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SAP-a program package for three-dimensional interconnect simulation

Cited by 6 publications

References 5 publications

Rigorous Capacitance Simulation of DRAM Cells

Rigorous Capacitance Simulation of DRAM Cells

Three-dimensional on-chip inductance and resistance extraction

Precise chip and package 3D capacitance simulations of realistic interconnects using a general purpose FEM-tool

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