SAT-ATPG for application-oriented FPGA testing

Hulle, Robert; Fišer, Petr; Schmidt, Jan; Borecky, Jaroslav

doi:10.1109/bec.2016.7743734

Cited by 7 publications

(9 citation statements)

References 23 publications

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“…There are cases in which some faults are missed because the method discussed in a previous study [12] is only considered "stack-at faults." Fault models for mapping a circuit to an LUT in an FPGA have been reported [20], [21]. Basically, the entity of a k-input LUT is a 2 k -bit SRAM cell.…”

Section: B Proposed Design Methods Of Tsc Comparators Implementable O...mentioning

confidence: 99%

“…Basically, the entity of a k-input LUT is a 2 k -bit SRAM cell. We can diagnosis a k-input LUT by using the 2 k test patterns as long as we observe the LUT output [20], [21]. Short circuits of wiring between two nets [22] are also nonnegligible due to the LUT-based circuits having a large degree of freedom of implementation due to the programmability of LUTs.…”

Section: B Proposed Design Methods Of Tsc Comparators Implementable O...mentioning

confidence: 99%

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Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs

Kanno

Toba

Shimamura

et al. 2020

IEEE Trans. VLSI Syst.

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In this article, we propose a method for designing online totally self-checking (TSC) comparators for TSC systems implementable on field-programmable gate arrays (FPGAs). This method can be used to conduct exhaustive online diagnostics of each lookup table (LUT), which involves mapping the fundamental components of the comparator, with a small number of test patterns by directly measuring output of each LUT. Our method drastically reduces the number of test patterns for exhaustive diagnosis on the order of the input number n [O(n)] (n is the input number to the comparator) while maintaining 100% coverage, even if we only know the specifications of the LUT without knowing its detailed structure. FPGAs will be easily applicable to systems that require high dependability. To confirm the soft error rate (SER) in a static random-access memory (SRAM)-based FPGA, we also conducted an experiment involving a single-event upset (SEU) caused by neutron radiation. For this experiment, we designed an FPGA implementation of 1575 identical dual-modular-redundant TSC comparators. The experiment was conducted for 10.4 h, and 34 errors were observed regarding such failures in comparator function. The evaluated SER for the TSC comparator with the proposed method was 0.055 FIT at sea level of New York City.

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Section: B Proposed Design Methods Of Tsc Comparators Implementable O...mentioning

confidence: 99%

Section: B Proposed Design Methods Of Tsc Comparators Implementable O...mentioning

confidence: 99%

Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs

Kanno

Toba

Shimamura

et al. 2020

IEEE Trans. VLSI Syst.

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“…The ADT of interconnect resources attempt to cover all given types of faults on nets, the signal paths constructed from multiple interconnect resources [4,5,19,20,21,22], rather than test each resource individually. Test strategies are categorized into three major types, including coding-based algorithms [2,8,14,15,16,21], SAT/SMT-based algorithms [3,9,17], and ATPG-related approaches [6,9,11,23,24]. Coding-based algorithms generate binary value assignments to the nets in a CUT using deterministic coding algorithms.…”

Section: Related Workmentioning

confidence: 99%

“…Modern FPGAs manufactured with latest process can contain over fifty billion transistors, and thus, faults within FPGAs are highly probable [1,4,5,6,7]. Application-dependent test (ADT) method is an exclusive test method for FPGAs that requires a routed user design as the circuit under test (CUT) [2,3,4,6,8,9,10,11]. It only tests configured resources on the CUT.…”

Section: Introductionmentioning

confidence: 99%

“…The goal of this paper, on the other hand, is to fully test the interconnect resources with minimum number of TCs. Satisfiability (SAT) and satisfiability modulo theory (SMT) are useful tools to obtain a viable solution for some complicated issues [9,17]. Utilizing SAT/SMT takes two steps, modelling the issue as formulas and solving the formulas.…”

Section: Introductionmentioning

confidence: 99%

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Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

He,

Lai

2024

IEICE Electron. Express

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An application dependent FPGA interconnect testing scheme is presented. The goal is to reduce the number of test configurations while keeping high fault coverage. Reduction is done by using SMT constraints that allow multiple nets as a group to use one input vector, so that the number of test configurations is reduced. Based on the complete fault model, a novel approach to generate SAT formulas, most notably dominant bridging faults, are explained to retain coverage. Experiments on FPGAs shown that this method yield on average 44% fewer configurations on circuits with 1000~100000 LUTs comparing with existing methods, with full fault coverage.

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