SAT-based ATPG testing of inter- and intra-gate bridging faults

Nakura, Toru; Tatemura, Yutaro; Fey, Görschwin; Ikeda, Makoto; Komatsu, Setsuko; Asada, Kunihiro

doi:10.1109/ecctd.2009.5275065

Cited by 2 publications

(1 citation statement)

References 15 publications

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“…It can be classified into: 1) intra-gate and inter-gate BF depending on where the BFs are constrained to occur; 2) single BF (SBF) and multiple BF (MBF) depending on how many BFs are considered simultaneously; 3) two-line BF (TBF) and multi-line BF (MLBF) depending on how many lines are involved in a BF; 4) feedback BF (FBF) and non-feedback BF (NFBF) depending on whether the fault sites are causal. In these BF classes, two-line single bridging fault (TSBF) is most commonly used [8] [9]. In addition, resistive bridging fault (RBF) is of great interest in VSLI testing in recent years.…”

Section: Introductionmentioning

confidence: 99%

Fault Models of CMOS Gates: An Empirical Study Based on Mutation Analysis

Tang

et al. 2014

2014 IEEE 12th International Conference on Dependable, Autonomic and Secure Computing

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An empirical study is conducted to analyze the fault models of CMOS gates in VLSI. The mutation analysis methodology is used to ensure the simulation experiments are sufficient enough. For the primitive CMOS logic cells: inverter, 2-input NAND, NOR and XOR gates, a total of 335 mutant circuits are generated, simulated and analyzed. Comparing with the previous work, several new fault models are revealed, such as other-logic and the indetermination fault category's subcategories: 0-to-X, 1-to-X and other-to-X. Besides, the experimental results show that the classic static stuck-at fault cannot cover many practical defects in a circuit since it just averagely accounts for less than 15% of the total faults. Many other useful conclusions are drawn, which may benefit the related fault-based applications.

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Section: Introductionmentioning

confidence: 99%

Fault Models of CMOS Gates: An Empirical Study Based on Mutation Analysis

Tang

et al. 2014

2014 IEEE 12th International Conference on Dependable, Autonomic and Secure Computing

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Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults

Mokhtarnia

Borujeni

Ehsani

2019

J CIRCUIT SYST COMP

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Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.

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SAT-based ATPG testing of inter- and intra-gate bridging faults

Cited by 2 publications

References 15 publications

Fault Models of CMOS Gates: An Empirical Study Based on Mutation Analysis

Fault Models of CMOS Gates: An Empirical Study Based on Mutation Analysis

Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults

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