SAT-Based Verification without State Space Traversal

Bjesse, Per; Claessen, Koen

doi:10.1007/3-540-40922-x_23

Cited by 106 publications

(91 citation statements)

References 11 publications

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“…For these designs, the number of flip-flops ranges from ~1K to ~13K and number of 2-input gates ranges from ~20K to ~0.5M. Out of 15 examples, 6 have counter examples and the rest do not have counterexample within the bound chosen. We used a Master (referred to as M) and 2 Clients (referred as C1 and C2) model where C1 and C2 can communicate with each other.…”

Section: Methodsmentioning

confidence: 99%

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Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking

Ganai¹,

Gupta²,

Yang³

et al. 2003

Lecture Notes in Computer Science

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Abstract. SAT-based Bounded Model Checking (BMC), though a robust and scalable verification approach, still is computationally intensive, requiring large memory and time. Interestingly, with the recent development of improved SAT solvers, it is frequently the memory limitation of a single server rather than time that becomes a bottleneck for doing deeper BMC search. Distributing computing requirements of BMC over a network of workstations can overcome the memory limitation of a single server, albeit at increased communication cost. In this paper, we present: a) a method for distributed-SAT over a network of workstations using a Master/Client model where each Client worsktation has an exclusive partition of the SAT problem and uses knowledge of partition topology to communicate with other Clients, b) a method for distributing SATbased BMC using the distributed-SAT. For the sake of scalability, at no point in the BMC computation does a single workstation have all the information. We experimented on a network of heterogenous workstations interconnected with a standard Ethernet LAN. To illustrate, on an industrial design with ~13K FFs and ~0.5M gates, the non-disributed BMC on a single workstation (with 4 Gb memory) ran out of memroy after reaching a depth of 120; on the otherhand, our SAT-based distributed BMC over 5 similar workstations was able to go upto 323 steps with a communication overhead of only 30%.

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Section: Methodsmentioning

confidence: 99%

“…Their performance is less sensitive to the problem sizes and they do not suffer from space explosion. As a result, various researchers have developed routines for performing Bounded Model Checking (BMC) using SAT [5][6][7][8]. Unlike symbolic model checking, BMC focuses on finding bugs of a bounded Fig.…”

Section: Introductionmentioning

confidence: 99%

Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking

Ganai¹,

Gupta²,

Yang³

et al. 2003

Lecture Notes in Computer Science

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show abstract

“…Two recent works [18,89] have proposed the use of more powerful forms of induction known as induction with depth and unique states induction to verify safety properties. For induction with depth n the formulas of Eq.…”

Section: Sat-based Inductive Reasoningmentioning

confidence: 99%

“…This frequently allows induction proofs to go through successfully. A related line of research is based on generating an inductive invariant to be used as overapproximation for the reachable states in the context of sequential equivalence checking [18,94,99].…”

Section: Sat-based Inductive Reasoningmentioning

confidence: 99%

A survey of recent advances in SAT-based formal verification

Prasad

Biere

Gupta³

2005

Int J Softw Tools Technol Transfer

204

120

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Abstract. Dramatic improvements in SAT solver technology over the last decade and the growing need for more efficient and scalable verification solutions have fueled research in verification methods based on SAT solvers. This paper presents a survey of the latest developments in SAT-based formal verification, including incomplete methods such as bounded model checking and complete methods for model checking. We focus on how the surveyed techniques formulate the verification problem as a SAT problem and how they exploit crucial aspects of a SAT solver, such as application-specific heuristics and conflict-driven learning. Finally, we summarize the noteworthy achievements in this area so far and note the major challenges in making this technology more pervasive in industrial design verification flows.

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“…This is mainly due to the fact that SAT algorithms have seen tremendous improvements in the last few years, allowing larger problem instances to be solved in different applications domains. Such applications include formal verification [1], FPGA routing [2], global routing [3], logic synthesis [4], sequential equivalence checking [5], and VLSI testing [6]. SAT has also been extended to a variety of applications in Artificial Intelligence including other well-known NP-complete problems such as graph colorability, vertex cover, and Hamiltonian path [7].…”

Section: Introductionmentioning

confidence: 99%

Using SAT-based techniques in power estimation

Sagahyroon

Aloul

2007

Microelectronics Journal

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Recent algorithmic advances in Boolean satisfiability (SAT), along with highly efficient solver implementations, have enabled the successful deployment of SAT technology in a wide range of applications domains, and particularly in electronic design automation (EDA). SAT is increasingly being used as the underlying model for a number of applications in EDA. This paper describes how to formulate two problems in power estimation of CMOS combinational circuits as SAT problems or 0-1 integer linear programming (ILP). In these circuits, it was proven that maximizing dissipation is equivalent to maximizing gate output activity, appropriately weighted to account for differing load capacitances. The first problem in this work deals with identifying an input vector pair that maximizes the weighted circuit activity. In the second application we attempt to find an estimate for the maximum power-up current in circuits where power cut-off or gating techniques are used to reduce leakage current. Both problems were successfully formulated as SAT problems. SAT-Based and generic Integer Linear Programming (ILP) solvers are then used to find a solution. The experimental results obtained on a large number of benchmark circuits provide promising evidence that the proposed complete approach is both viable and useful and outperforms the random approach. r

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SAT-Based Verification without State Space Traversal

Cited by 106 publications

References 11 publications

Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking

Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking

A survey of recent advances in SAT-based formal verification

Using SAT-based techniques in power estimation

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