SAT Sweeping with Local Observability Don’t-Cares

Zhu, Qi; Kitchen, Nathan; Kuehlmann, Andreas; Sangiovanni-Vincentelli, A.

doi:10.1007/978-1-4419-7518-8_8

Cited by 4 publications

(4 citation statements)

References 14 publications

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“…AIG is a way of representing Boolean function manipulation. The technique has been widely used in technology mapping, logic synthetic, and verification [15], [16], [17], [18], [19].…”

Section: Related Workmentioning

confidence: 99%

Optimising simulation data structures for the Xeon Phi

Chimeh

Cockshott

2016

2016 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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In this paper, we propose a lock-free architecture to accelerate logic gate circuit simulation using SIMD multi-core machines. We evaluate its performance on different test circuits simulated on the Intel Xeon Phi and 2 other machines. Comparisons are presented of this software/hardware combination with reported performances of GPU and other multi-core simulation platforms. Comparisons are also given between the lock free architecture and a leading commercial simulator running on the same Intel hardware.

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“…AIG is a way of representing Boolean function manipulation. The technique has been widely used in technology mapping, logic synthetic, and verification [15], [16], [17], [18], [19].…”

Section: Related Workmentioning

confidence: 99%

Optimising simulation data structures for the Xeon Phi

Chimeh

Cockshott

2016

2016 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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“…Disadvantage 2 CNF SAT solvers are restricted to using optimizations, such as symmetry breaking [22] and observability don't cares (ODC) [23], that apply at the level of CNF formulae. However these optimizations usually aim at increasing the speed of the solver and often result in larger formulae as they add literals and clauses to the CNF formula to encode symmetry and ODC optimizations [24]. Often times when the analyzer successfully generates a large CNF formula, the underlying solver requires intractable resources.…”

Section: Disadvantagementioning

confidence: 99%

Model Checking Software Programs with First Order Logic Specifications using AIG Solvers

Zaraket,

Noureddine

2014

Preprint

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Static verification techniques leverage Boolean formula satisfiability solvers such as SAT and SMT solvers that operate on conjunctive normal form and first order logic formulae, respectively, to validate programs. They force bounds on variable ranges and execution time and translate the program and its specifications into a Boolean formula. They are limited to programs of relatively low complexity for the following reasons. (1) A small increase in the bounds can cause a large increase in the size of the translated formula. (2) Boolean satisfiability solvers are restricted to using optimizations that apply at the level of the formula. Finally, (3) the Boolean formulae often need to be regenerated with higher bounds to ensure the correctness of the translation.We present a method that uses sequential circuits, Boolean formulae with memory elements and hierarchical structure, and sequential circuit synthesis and verification frameworks to validate programs. (1) Sequential circuits are much more succinct than Boolean formulae with no memory elements and preserve the high-level structure of the program. (2) Encoding the problem as a sequential circuit enables the use of a number of powerful automated analysis techniques that have no counterparts for other Boolean formulae. Our method takes an imperative program with a first order logic specification consisting of a precondition and a postcondition pair, and a bound on the program variable ranges, and produces a sequential circuit with a designated output that is true when the program violates the specification. Our method uses sequential circuit synthesis reduction techniques to reduce the generated circuit, and then uses sequential circuit verification techniques to check the satisfiability of the designated output. The results show that our method can validate designs that are not possible with other state of the art techniques, and with bounds that are an order of magnitude larger.

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“…Improving the efficiency of SAT solvers with circuit observability don't cares has been explored previously [8,10,35,34,36]. In [10], ODCs are used to mark clauses as inactive which are removed dynamically from the CNF.…”

Section: Incorporating Odcs With Sat Solversmentioning

confidence: 99%

“…The techniques introduced by [34,8] recognize the benefits of ODCs as it incorporates this information directly in the problem CNF by introducing don't care literals. The work of [36] finds and exploits ODCs during SAT sweeping to simplify the problem representation.…”

Section: Incorporating Odcs With Sat Solversmentioning

confidence: 99%

Improved SAT-based Reachability Analysis with Observability Don’t Cares

Safarpour

Veneris

Drechsler³

2008

SAT

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The dramatic performance improvements of SAT solvers over the past decade have increased their deployment in hardware verification applications. Many problems that were previously too large and complex for SAT techniques can now be handled in an efficient manner. One such problem is reachability analysis, whose instances are found throughout verification applications such as unbounded model checking and trace reduction. In circuitbased reachability analysis important circuit information is often lost during the circuitto-SAT translation process. Observability Don't Cares (ODCs) are an example of such information that can potentially help achieve better and faster results for the SAT solver. This work proposes to use the ODCs to improve the quality and performance of SATbased reachability analysis frameworks. Since ODCs represent variables whose values do not affect the outcome of a problem, it is possible to satisfy a problem with fewer assigned variables. This in turn leads to more compact solutions and thus fewer solutions to cover the entire solution space. Specifically, this work presents an efficient way to identify ODCs, proves the correctness of leaving ODC variables unassigned, and develops a reachability analysis platform that benefits greatly from the ODCs. The advantages of using ODCs in reachability analysis is demonstrated through extensive experiments on unbounded model checking and trace reduction applications.

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SAT Sweeping with Local Observability Don’t-Cares

Cited by 4 publications

References 14 publications

Optimising simulation data structures for the Xeon Phi

Optimising simulation data structures for the Xeon Phi

Model Checking Software Programs with First Order Logic Specifications using AIG Solvers

Improved SAT-based Reachability Analysis with Observability Don’t Cares

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