SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder

Silveira, Eianca; Diniz, Cláudio M.; Fonseca, Mateus Beck; Costa, Eduardo

doi:10.1109/icecs.2015.7440382

Cited by 11 publications

(6 citation statements)

References 12 publications

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“…The performance comparison is shown in Table 2. Based on the comparison, the utilization ratio is quite similar but our architecture can run at 267.52 MHz, which is 1.4x faster than [18] which is running at 188 MHz.…”

Section: Results and Analysismentioning

confidence: 95%

“…Most of the literature work have implemented their design onto an ASIC. As to the authors knowledge, only the work in [18] presented their results on FPGA. However, their implementation is on Altera FPGA, while our implementation is on Xilinx FPGA.…”

Section: Results and Analysismentioning

confidence: 99%

“…The work in [18] presents an architecture for an 8x8 Hadamard transform, mainly used for ultrahigh resolution video sequence. Compared to a 4x4 transform, the 8x8 transform results in 9% to 19% less total execution time for these types of video.…”

Section: Introductionmentioning

confidence: 99%

“…Pipelining results in higher performance, while feedthrough control allows variable throughput depending on the input block size. The designs are synthesized and implemented on Xilinx Kintex Ultrascale device, and compared with the work in [18] using Altera FPGA.…”

Section: Introductionmentioning

confidence: 99%

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Hardware design of a scalable and fast 2-D hadamard transform for HEVC video encoder

Ney

Rahman

Awab

et al. 2019

IJEECS

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<span>This paper presents the hardware design of a 2-dimensional Hadamard transform used the in the rate distortion optimization module in state-of-the-art HEVC video encoder. The transform is mainly used to quickly determine optimum block size for encoding part of a video frame. The proposed design is both scalable and fast by 1) implementing a unified architecture for sizes 4x4 to 32x32, and 2) pipelining and feed through control that allows high performance for all block sizes. The design starts with high-level algorithmic loop unrolling optimization to determine suitable level of parallelism. Based on this, a suitable hardware architecture is devised using transpose memory buffer as pipeline memory for maximum performance. The design is synthesized and implemented on Xilinx Kintex Ultrascale FPGA. Results indicate variable performance obtained for different block sizes and higher operating frequency compared to a similar work in literature. The proposed design can be used as a hardware accelerator to speed up the rate distortion optimization operation in HEVC video encoders.</span>

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Section: Results and Analysismentioning

confidence: 95%

Section: Results and Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Hardware design of a scalable and fast 2-D hadamard transform for HEVC video encoder

Ney

Rahman

Awab

et al. 2019

IJEECS

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“…An efficient integer motion estimation hardware approach was proposed with a low latency reduction of 80% [8]. Eianca Silveira adopted a structure for the Sum of Absolute Transform Differences (SATD), which consumes 50.85pJ for a single SATD [9].…”

Section: Introductionmentioning

confidence: 99%

Hardware motion estimation methods survey and example real-time architecture design

Zhong

2024

ACE

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Motion estimation is essential in video processing, computer vision, and other related fields due to its applications in improving data compression, enhancing image/video quality, increasing computer vision task accuracy, and conserving computational resources. Typical motion estimation methods include FS (Full Search) and DS (Diamond Search). Traditional motion estimation methods will face the challenge of high complexity in practical real-time applications. Therefore, this paper focuses on fast motion estimation algorithms and hardware architecture design for real-time applications survey and research. Aiming at the need for 1920x1080@60fps processing speed, this paper explores the key ideas of FS and DS hardware structure design based on the Vivado HLS high-level synthesis tool and provides a feasible hardware scheme to meet the real-time requirements.

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The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures

Silveira

Paim

Abreu

et al. 2021

Circuits Syst Signal Process

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SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder

Cited by 11 publications

References 12 publications

Hardware design of a scalable and fast 2-D hadamard transform for HEVC video encoder

Hardware design of a scalable and fast 2-D hadamard transform for HEVC video encoder

Hardware motion estimation methods survey and example real-time architecture design

The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures

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