Scalable 2-bit silicon–oxide–nitride–oxide–silicon (SONOS) memory with physically separated local nitrides under a merged gate

Lee, Yong Kyu; Sung, Soonchang; Sim, Jae Sung; Song, Ki Whan; Lee, Jong Duk; Park, Byung‐Gook; Kang, Sung Taeg; Chung, Chilhee; Park, Donggun; Kim, Kinam

doi:10.1016/j.sse.2004.05.048

Cited by 5 publications

(4 citation statements)

References 4 publications

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“…Although the wide charge distribution is observed in the present device, such a problem can be reduced by optimizing the structure so that two trap sites in the nitride can be physically separated from each other. 20) This information pertaining to the trapped charges and interface states at each level of the four states helps not only further understand the transient characteristics of CHE injections during 4-bit operations, but also optimize the program conditions for reliable 4-bit/cell SONOS operations.…”

Section: Discussionmentioning

confidence: 99%

A Direct Observation of the Distributions of Local Trapped-Charges and the Interface-States near the Drain Region of the Silicon–Oxide–Nitride–Oxide–Silicon Device for Reliable Four-Bit/Cell Operations

Zhang

Kim

et al. 2010

Jpn. J. Appl. Phys.

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This paper reports the direct observation of the threshold voltage shifts with trapped-charge densities as well as the interface-state densities after 10 4 program/erase (P/E) cycles at each state of the four levels in the drain edge of the silicon-oxide-nitride-oxide-silicon (SONOS) structure. We prepared a SONOS device with a 3.4-nm-thick tunnel oxide, showing 2-bit and 4-level operations at program voltages of 4 -6 V, with a 10-year retention and 10 4 P/E endurance properties. Then, by using charge pumping methods, we observed the vertical and the lateral distributions of the trapped-charges and their interface-states with the gate biases at each level of the four states in the drain edge. The trapped-charges densities at the ''10'', ''01'', and ''00'' states in the drain region were estimated to be 1:4 Â 10 12 , 3:0 Â 10 12 , and 4:9 Â 10 12 cm À2 , respectively, with a lateral width of 220 nm. The peak location of the interface-state density was shifted from the drain edge to the channel with an increase in the gate bias. These observations will be quite useful to optimize the program conditions for reliable 4-bit/cell SONOS operations.

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Section: Discussionmentioning

confidence: 99%

A Direct Observation of the Distributions of Local Trapped-Charges and the Interface-States near the Drain Region of the Silicon–Oxide–Nitride–Oxide–Silicon Device for Reliable Four-Bit/Cell Operations

Zhang

Kim

et al. 2010

Jpn. J. Appl. Phys.

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“…To mitigate the aforementioned issues, silicon nitride (Si 3 N 4 ) with discrete charge-trapping sites has been introduced to replace poly-Si floating gate as the charge-trapping layer and this is the Manuscript well-known silicon-oxide-nitride-oxide-silicon (SONOS) memory structure. SONOS-type flash memories have soon attracted a lot of attention [1]- [3] due to their advantages over the conventional floating gate flash memory device in terms of higher chip density, higher operation speed, better data retention, lower operation voltage, and even 2-bit operation [4], [5]. To further improve the memory device performance for SONOS memory devices, a high-permittivity (high-κ) dielectric has been recently substituted for the Si 3 N 4 film as the charge-trapping layer since it usually possesses a larger conduction band offset ΔEc with respect to the tunnel dielectric and, thus, better charge retention.…”

Section: Introductionmentioning

confidence: 99%

Electrical Characteristics for Flash Memory With Germanium Nitride as the Charge-Trapping Layer

Lin

et al. 2013

IEEE Trans. Nanotechnology

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Due to a larger band offset and a higher permittivity compared to Si 3 N 4 , Ge 3 N 4 formed by NH 3 plasma nitridation of an amorphous Ge film was explored in this study as the chargetrapping layer for flash memory devices. As the nitridation time prolongs, memory window and operation speed are improved accordingly. The improvement is inferred to be the increased number of trapping sites and higher permittivity of the charge-trapping layer caused by the introduction of nitrogen atoms. The former is helpful in storing more charges while the latter offers a higher electric field over the tunnel oxide. Memory devices with 180-s NH 3 plasma nitridation hold great potential for advanced memory applications because they possess many promising characteristics such as a large hysteresis memory window, high operation speed, robust endurance performance up to 10 5 program/erase (P/E) cycles, and good retention characteristic with 15% charge loss after 10-year operation at 85 • C.

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“…8 High quality thin films of HfO 2 and TiO 2 have been formed by using different systems, such as metal organic chemical vapor deposition, reactive sputtering and atomic layer deposition. [9][10][11][12][13] In general, these studies show that amorphous HfO 2 and TiO 2 films could be produced at relatively low temperatures with good deposition rates. Previous studies have focused on film qualities, such as film thickness/deposition rate, structural/compositional properties, morphology and electrical properties.…”

Section: Introductionmentioning

confidence: 99%

Structural and dielectric characterization of atomic layer deposited HfO<inf>2</inf> and TiO<inf>2</inf> as promising gate oxides

Tao

Jursich

Takoudis

2010

2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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Tetrakis (diethylamino) hafnium (TDEAH), tetrakis (diethylamino) titanium (TDEAT) and H 2 O were used for the atomic layer deposition of HfO 2 and TiO 2 films on silicon substrates. X-ray Photoelectron Spectroscopy showed that after a short Ar + sputtering for removing surface contaminants, both HfO 2 and TiO 2 films were found to be essentially carbon free. While HfO 2 remained at +4 chemical state after the surface sputtering, TiO 2 partially changed into Ti +3 (Ti 2 O 3 ) and Ti +2 (TiO), suggesting a preferential sputtering of O over Ti. Phase-shift interferometry (PSI) was applied to probe the surface morphology of both as-deposited and post annealed films, which were later examined by Grazing Incidence X-ray Diffraction (GIXRD). From both PSI and GIXRD results, as-deposited HfO 2 and TiO 2 films were found to be amorphous with smooth surfaces but began to crystallize with roughened surfaces after annealing at 600 °C, with HfO 2 crystallizing into a monoclinic structure and TiO 2 crystallizing into an anatase structure. C-V and I-V measurement were performed after electron beam evaporation of Al metal contacts on the dielectric layers. The calculated dielectric constant (k) value of TiO 2 is almost three times higher than that of HfO 2 and the measured leakage current densities for the metal oxides are below 10 -5 A/cm 2 at the applied voltage of 1 V.

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Scalable 2-bit silicon–oxide–nitride–oxide–silicon (SONOS) memory with physically separated local nitrides under a merged gate

Cited by 5 publications

References 4 publications

A Direct Observation of the Distributions of Local Trapped-Charges and the Interface-States near the Drain Region of the Silicon–Oxide–Nitride–Oxide–Silicon Device for Reliable Four-Bit/Cell Operations

A Direct Observation of the Distributions of Local Trapped-Charges and the Interface-States near the Drain Region of the Silicon–Oxide–Nitride–Oxide–Silicon Device for Reliable Four-Bit/Cell Operations

Electrical Characteristics for Flash Memory With Germanium Nitride as the Charge-Trapping Layer

Structural and dielectric characterization of atomic layer deposited HfO<inf>2</inf> and TiO<inf>2</inf> as promising gate oxides

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