Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology

Tan, Xiao; Zhang, Lei; Neelkrishnan, Shankar; Yang, Mei; Jiang, Yingtao; Yang, Yue

doi:10.1145/1366110.1366184

Search citation statements

Order By: Relevance

Paper Sections

Select...

Recursive Diagonal Torus1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2013

2016

Publication Types

Select...

Article1

Other1

Relationship

Self Cite0

Independent2

Authors

Journals

Cited by 2 publications

(1 citation statement)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Their evaluation shows that the packet latency degrades gracefully. Tan et al [2008] dealt with the implementation of a shortest path routing algorithm for QRDT, codenamed Johnson Coded Vector Routing (JCVR). By applying minor modifications of their algorithm, they show that it is capable of handling single link/node faults.…”

Section: Recursive Diagonal Torusmentioning

confidence: 99%

A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip

2016

View full text Add to dashboard Cite

Increasing fault rates in current and future technology nodes coupled with on-chip components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) designs. Given the central role of NoCs in today's many-core chips, permanent faults impeding their original functionality may significantly influence performance, energy consumption, and correct operation of the entire system. As a result, fault-tolerant NoC design gained much attention in recent years. In this article, we review the vast research efforts regarding a NoC's components, namely, topology, routing algorithm, router microarchitecture, as well as system-level approaches combined with reconfiguration; discuss the proposed architectures; and identify outstanding research questions.

show abstract

Section: Recursive Diagonal Torusmentioning

confidence: 99%