This paper presents a parameterized router design which can be applied to build large network-on-chips (NoCs) based on a Perfect Recursive Diagonal Torus (PRDT) IntroductionAs predicted by the International Technology Roadmap for Semiconductors (ITRS) [8], for the next 5 to 10 years, System-on-Chips (SoCs), using 32nm transistors operating below one volt, will grow to multi-billion transistors running at a frequency of 10GHz or higher. One of the major challenges in designing such highly integrated SoCs will be to find an effective way to integrate pre-designed Intellectual Property (IP) cores for power and performance concerns [1]. As the device feature size is continuously shrinking and the bandwidth requirements are increasing, traditional bus-based SoC architectures [1] have been found creating a performance bottleneck. Network-on-Chips (NoCs) thus have emerged as a promising alternative to overcome those limitations of bus-bused architectures by employing a packet-based micro-network for inter-IP communication.In general, a packet-based NoC consists of routers, the network interface between the routers and the IP, and the interconnection network. The major challenges faced by NoC designs include scalability, energy efficiency, and reconfigurability [3]. In designing an NoC system, the interconnection network is the key in addressing these challenges. Numerous interconnection network topologies have been considered for NoCs, including mesh [10], torus [9], fat tree [5], honeycomb [6], and a few others [3]. However, the aforementioned interconnection topologies are either not scalable or not reconfigurable. To address these two problems, a novel class of topologies named Recursive Diagonal Torus (RDT) [16] is proposed for NoCs [17]. The RDT structure is constructed by recursively overlaying 2-D diagonal torus, and it has the following features: recursive structure with constant node degree, smaller diameter and average distance, and embedded mesh/torus topology. A special type of RDT, called Perfect RDT (PRDT) [14] is considered to be a promising on-chip interconnection network topology due to its symmetric structure and simpler link connections than other RDT structures.As the interface of an IP to the on-chip interconnection network, the router design has an important impact to the cost and performance a NoC design. In the literature, a number of NoC router designs have been proposed, such as MANGO router [18], ParIS [2]. However, these routers are tailored for a particular topology and cannot be directly applied to PRDT(2,1)-based NoCs. This paper is focused on developing a parameterized router for PRDT-based NoCs in hardware. As PRDT can be considered as a variation of torus, the router, although designed and optimized for PRDT, is reconfigurable to be applied to build mesh/torus-based NoCs. In specific, the router implements two routing algorithms (vector routing and Johnson coded vector routing), the wormhole switching scheme, the scheduling scheme, buffering strategy, and flow control scheme...

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