Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Abstract

Abstract-The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel, scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the Logic BIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target Fault Coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared to recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

“…Please note that in cases when the presumed offset Θ is known, Table 2 makes it possible to find out 𝑛 and 𝑡 parameters of the appropriate DT-LFSR register to enable designing of a TPG that is able to supply test sequences to any number of scan paths, or at least as many as practicable. 15 6.21×10 14 3.11×10 14 1.55×10 14 7.76×10 13 3.88×10 13 12 59 60 1.53×10 14 7.63×10 13 3.82×10 13 1.91×10 13 9.54×10 12 4.77×10 12 13 59 68 3.91×10 16 1.95×10 16 9.77×10 15 4.89×10 15 2.44×10 15 1.22×10 15 14 62 63 1.16×10 15 5.81×10 14 2.91×10 14 1.45×10 14 7.26×10 13 3.63×10 13 15 62 71 2.98×10 17 1.49×10 17 7.44×10 16 3.72×10 16 1.86×10 16 9.30×10 15 16 65 71 2.84×10 17 1.42×10 17 7.09×10 16 3.55×10 16 1.77×10 16 8.87×10 15 17 65 81 2.91×10 20 1.45×10 20 7.27×10 19 3.63×10 19 1.82×10 19 9.08×10 18 18 70 79 6.75×10 19 3.37×10 19 1.69×10 19 78 95 3.97×10 24 1.98×10 24 9.92×10 23 4.96×10 23 2.48×10 23 1.24×10 23 22 84 95 3.68×...…”

“…On the contrary, the figures from Table 5 indicate that the phase shift (separation factor for output channels) enabled by the DT-LFSR Test Pattern Generator (DT-LFSR-TPG) for a specific number of scan chains can be higher by several magnitudes than numbers offered by LFSR+PS and CA+PS solutions disclosed in aforementioned studies. 25 7.28×10 24 3.64×10 24 1.82×10 24 9.10×10 23 4.55×10 23 2.28×10 23 24 91 1.36×10 25 6.80×10 24 3.40×10 24 1.70×10 24 8.50×10 23 4.25×10 23 2.13×10 23…”

“…There are numerous studies where researchers make efforts to improve the solution in terms of hardware overhead, testing time, power consumption, fault coverage, diagnosability, etc. [17][18][19][20][21][22][23][24][25][26]. Some variations of the STUMPS architecture are implemented into hybrid LBIST, where pseudo-random testing is combined with deterministic testing or test data compression [27][28][29][30][31][32].…”

Using Fuzzy Logic to Control Dynamic Loads on Road-Building Machine Construction Elements

“…The formalization of linguistic meanings within the theory of fuzzy sets is carried out through membership functions (MFs) . The most widespread methods of constructing MFs are based on the statistical processing of expert information and on paired comparisons [4][5][6][18][19][20][21][22][23]. These methods are mainly used in the development of pure expert systems that apply only expert knowledge [7][8][9][10].…”