This thesis documents the compact model development for the silicon nanowire MOSFET. A surface-potential based scalable model is developed for silicon nanowire MOSFET. An accurate surface potential initial guess is derived for the iterative surface potential solution within a few iteration steps. An analytical single-piece expression of the surface potential solution is derived in all regions of operation. An intrinsic long channel transistor drain current model is developed as the core model without chargesheet approximation. To extend the core model into short channel devices, many physical phenomena including mobility degradation, channel length modulation, velocity saturation, and drain induced barrier lowering are incorporated into the core model. Some threshold voltage definitions are discussed and a new threshold voltage expression is proposed for silicon nanowire MOSFETs. The threshold voltage roll-off, subthreshold slope degradation, and drain induced barrier lowing effects are modeled with an approximate solution of the 2D Poisson's equation. A simple, accurate, and continuous charge and capacitance model is developed based on the single-piece drain current model.