ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) 2021
DOI: 10.1109/esscirc53450.2021.9567887
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Scalable Digital Synchronizer for Enabling Hardware-Level BLE Mesh Networks under 1 mW

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Cited by 2 publications
(5 citation statements)
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“…Figure 9 shows the functional top-level block diagram of the implemented P2P radio node that is based on prior work in [ 16 ]. Each node comprises a custom RF (radio frequency) board with an AD9364 transceiver (the radio), a crystal oscillator and miscellaneous support circuitry, the ASIC accelerator chip, and a ZedBoard.…”
Section: Synchronization Analysis and Requirementsmentioning
confidence: 99%
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“…Figure 9 shows the functional top-level block diagram of the implemented P2P radio node that is based on prior work in [ 16 ]. Each node comprises a custom RF (radio frequency) board with an AD9364 transceiver (the radio), a crystal oscillator and miscellaneous support circuitry, the ASIC accelerator chip, and a ZedBoard.…”
Section: Synchronization Analysis and Requirementsmentioning
confidence: 99%
“…The signal processing core is able to detect the syncword regardless of the phase and frequency mismatch between the TX and the RX local oscillators (LOs). Prior works describe in detail the operations performed by the signal processing core [ 14 , 16 ]. If the syncword is detected, the state of the PCO is advanced.…”
Section: Synchronization Analysis and Requirementsmentioning
confidence: 99%
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