Scalable fabrication of self-assembled GeSn vertical nanowires for nanophotonic applications

Abstract

In this work, scalable fabrication of self-assembled GeSn vertical nanowires (NWs) based on rapid thermal annealing (RTA) and inductively coupled-plasma (ICP) dry etching was proposed. After thermal treatment of molecular-beam-epitaxy-grown GeSn, self-assembled Sn nanodots (NDs) were formed on surface and the spontaneous emission from GeSn direct band was enhanced by ∼5-fold. Employing the self-assembled Sn NDs as template, vertical GeSn NWs with a diameter of 25 ± 6 nm and a density of 2.8 × 109 cm−2 were obtained by Cl-based ICP dry etching technique. A prototype GeSn NW photodetector (PD) with rapid switching ability was demonstrated and the optoelectronic performance of Ge NW PD was systematically studied. The GeSn NW PD exhibited an ultralow dark current density of ∼33 nA/cm2 with a responsivity of 0.245 A/W and a high specific detectivity of 2.40 × 1012 cm Hz1/2 W−1 at 1550 nm under −1 V at 77 K. The results prove that this method is prospective for low-cost and scalable fabrication of GeSn NWs, which are promising for near infrared or short wavelength infrared nanophotonic devices.

Research progress of out-of-plane GeSn nanowires

“…Therefore, a strain-relaxed Ge buffer layer (Ge virtual substrate (VS)) needs to be deposited on the Si substrate as a template for GeSn epitaxy. GeSn NWs are typically grown using the top-down approach in three phase [59][60][61][62][63][64][65]. In the first step, a strain-free Ge buffer layer and GeSn layer are deposited on Si substrate by either CVD mechanism or MBE mechanism, and the Sn content in the GeSn layer determines the Sn content in the GeSn NWs prepared by the top-down method, and thickness of the Ge-VS layer and GeSn layer almost determine the minimum length of out-of-plane vertical GeSn NWs.…”

“…In the second step, arrays with variable NW diameters and pitch lengths were patterned by photolithography. For the fabrication of self-assembled GeSn NWs, Sn nanodots, which are produced from the GeSn layer by rapid thermal annealing (RTA) treatment, can be employed as hard masks [62,63]. In the third step, GeSn NW arrays are prepared by inductively coupled plasma reactive ion etching (ICP-RIE) with Cl-based or F-based chemistries [65,67].…”

“…In addition, periodic digital etching, which consists of selflimited O 2 plasma and HF rinse to remove oxide, can further reduce the diameter of NWs precisely [61,64] while minimizing the damage caused by RIE and fabricating GeSn NW with an anisotropic profile and smooth sidewall. The fabrication process of self-assembled GeSn vertical NWs is depicted in figures 2(a)-(c) [62]. The initial GeSn samples (figure 2(a)) were through RTA process (figure 2(b)) and the ICP dry etching procedure (figure 2(c)), eventually forming the out-ofplane GeSn NWs.…”

“…Currently, the application of out-of-plane GeSn NWs is still in the phase of basic research and technology development. However, the literature indicates that out-of-plane GeSn NWs have many potential applications, especially as infrared photodetectors [55,62,91,159,162,[166][167][168], high-efficiency Li-ion battery anodes [122], nanowire SWIR lasers [152,169,170], nanowire transistors (figure 8) [55,60,61,[171][172][173][174][175].…”

“…Recently, Lin et al fabricated self-assembled vertical GeSn NWs based on RTA and ICP dry etching and investigated their optoelectronic properties [62]. They found that these NWs can be used as a prototype GeSn NW photodetector with fast switching capability.…”