Scalable FPGA-array for high-performance and power-efficient computation based on difference schemes

Sano, Kentaro; Wang, Luzhou; Hatsuda, Yoshiaki; Yamamoto, Satoru

doi:10.1109/hprcta.2008.4745679

Cited by 1 publication

(4 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…You can find their details in [14,15]. We solve the heat-conduction problem on a 2D square plate with the red-black-SOR (successive over-relaxation) method, RB-SOR.…”

Section: Benchmark Programsmentioning

confidence: 99%

“…As reported in [13][14][15], stencil computation is typically formed with a weighted sum of the neighboring values, which is as follows for the 3 × 3 stencil:…”

Section: Stencil Computationmentioning

confidence: 99%

“…(1) [13][14][15]. SCM architecture is the combination of the programmable systolic architecture [7,8] and the computational memory approach [4,11,12,18].…”

Section: Architecturementioning

confidence: 99%

“…So far we have proposed the systolic computationalmemory (SCM) architecture for scalable CCMs dedicated to stencil computation [13][14][15], which is one of the programmable systolic arrays performing floating-point operations. Theoretically the SCM architecture is designed to exploit the parallelism of the stencil computation by increasing the size of an SCM array (SCMA).…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation

Sano

Wang

Yamamoto

2010

SIGARCH Comput. Archit. News

Self Cite

View full text Add to dashboard Cite

This paper demonstrates and evaluates the performance and the scalability of the systolic computational-memory array (SCMA) for stencil computation, which is a typical computing kernel of scientific simulation. We describe the basic architecture of th SCMA, and show the requirements and the design of SCMAs to scalably operate over multiple devices. We implement a prototype of the SCMA with three ALTERA Stratix III FPGAs, which form a 1 × 3 FPGA array by conecting three DE3 boards with different clock sources. The prototype SCMA demonstrates that the difference in operating clock frequency hardly influences the total execution cycles while it slightly causes stall cycles to sub-SCMAs on different FPGAs. With three banchmark programs of typical computing kernels based on the finite difference method, we show that the increased FPGAs provide higher performance proportional to the number of devices, resulting in almost linear speedup.

show abstract

“…You can find their details in [14,15]. We solve the heat-conduction problem on a 2D square plate with the red-black-SOR (successive over-relaxation) method, RB-SOR.…”

Section: Benchmark Programsmentioning

confidence: 99%

“…As reported in [13][14][15], stencil computation is typically formed with a weighted sum of the neighboring values, which is as follows for the 3 × 3 stencil:…”

Section: Stencil Computationmentioning

confidence: 99%

“…(1) [13][14][15]. SCM architecture is the combination of the programmable systolic architecture [7,8] and the computational memory approach [4,11,12,18].…”

Section: Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations