Scalable IP lookup for programmable routers

Taylor, David E.; Lockwood, John W.; Sproull, Todd; Turner, Jon; Parlour, David B.

doi:10.1109/infcom.2002.1019301

Cited by 45 publications

(33 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Accesses to SRAM and SDRAM can take a significant amount of time which can increase the overall processing cost of TSA. We have used a multibit trie implementation [22] to reduce the number of memory accesses necessary to traverse the anonymization tree. Our current prototype runs on an Intel IXP 2400 network processor [7] and requires 4 accesses to the anonymization data structures instead of 26.…”

Section: Methodsmentioning

confidence: 99%

High-Speed Prefix-Preserving IP Address Anonymization for Passive Measurement Systems

Ramaswamy

Wolf

2007

IEEE/ACM Trans. Networking

View full text Add to dashboard Cite

Abstract-Passive network measurement and packet header trace collection are vital tools for network operation and research. To protect a user's privacy, it is necessary to anonymize header fields, particularly IP addresses. To preserve the correlation between IP addresses, prefix-preserving anonymization has been proposed. The limitations of this approach for a highperformance measurement system are the need for complex cryptographic computations and potentially large amounts of memory. We propose a new prefix-preserving anonymization algorithm, top-hash subtree-replicated anonymization (TSA), that features three novel improvements: precomputation, replicated subtrees, and top hashing. TSA makes anonymization practical to be implemented on network processors or dedicated logic at Gigabit rates. The performance of TSA is compared with a conventional cryptography based prefix-preserving anonymization scheme which utilizes caching. TSA performs better as it requires no online cryptographic computation and a small number of memory lookups per packet. Our analytic comparison of the susceptibility to attacks between conventional anonymization and our approach shows that TSA performs better for small scale attacks and comparably for medium scale attacks. The processing cost for TSA is reduced by two orders of magnitude and the memory requirements are a few Megabytes. The ability to tune the memory requirements and security level makes TSA ideal for a broad range of network systems with different capabilities.

show abstract

Section: Methodsmentioning

confidence: 99%

High-Speed Prefix-Preserving IP Address Anonymization for Passive Measurement Systems

Ramaswamy

Wolf

2007

IEEE/ACM Trans. Networking

View full text Add to dashboard Cite

show abstract

“…Previously published hardware implementations based on the Tree Bitmap algorithm are the reference implementation of [5] and the low-cost oriented solution of [9]. The former implementation achieves 25 million lookups per second using a four times replicated forwarding table stored in external DRAM and an Application-Specific Integrated Circuit (ASIC) to implement the required logic.…”

Section: Fig 2 Ip Lookup Table In Tree Bitmap Representationmentioning

confidence: 99%

“…In order to investigate whether and with what effort algorithmic IP lookup modules can be realized in hardware for future line speeds of 100 Gbps and beyond, we clearly focused on maximum throughput and resource efficiency, as opposed to other published Tree Bitmap implementations [5,9]. By processing all packets in a pipeline, our design effectively performs one IP address lookup in each clock cycle.…”

Section: Introductionmentioning

confidence: 99%

A Pipelined IP Address Lookup Module for 100 Gbps Line Rates and beyond

Teuchert

Hauger

2009

The Internet of the Future

View full text Add to dashboard Cite

Abstract. New Internet services and technologies call for higher packet switching capacities in the core network. Thus, a performance bottleneck arises at the backbone routers, as forwarding of Internet Protocol (IP) packets requires to search the most specific entry in a forwarding table that contains up to several hundred thousand address prefixes. The Tree Bitmap algorithm provides a well-balanced solution in respect of storage needs as well as of search and update complexity. In this paper, we present a pipelined lookup module based on this algorithm, which allows for an easy adaption to diverse protocol and hardware constraints. We determined the pipelining degree required to achieve the throughput for a 100 Gbps router line card by analyzing a representative sub-unit for various configured sizes. The module supports IPv4 and IPv6 configurations providing this throughput, as we determined the performance of our design to achieve a processing rate of 178 million packets per second.

show abstract

“…Although TCAMbased engines can retrieve IP lookup results in just one clock cycle, their throughput is limited by the relatively low speed of TCAMs. They are expensive and offer little flexibility for adapting to new addressing and routing protocols [4]. As shown in Table I, SRAM outperforms TCAM with respect to speed, density and power consumption.…”

Section: Introductionmentioning

confidence: 99%

Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup

Jiang¹,

Wang²,

Prasanna³

2008

2008 Proceedings IEEE INFOCOM - The 27th Conference on Computer Communications

View full text Add to dashboard Cite

Abstract-Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of today's high-end routers, they do not scale well for the next-generation [1]. On the other hand, pipelined SRAMbased algorithmic solutions become attractive. Intuitively multiple pipelines can be utilized in parallel to have a multiplicative effect on the throughput. However, several challenges must be addressed for such solutions to realize high throughput. First, the memory distribution across different stages of each pipeline as well as across different pipelines must be balanced. Second, the traffic on various pipelines should be balanced.In this paper, we propose a parallel SRAM-based multipipeline architecture for terabit IP lookup. To balance the memory requirement over the stages, a two-level mapping scheme is presented. By trie partitioning and subtrie-to-pipeline mapping, we ensure that each pipeline contains approximately equal number of trie nodes. Then, within each pipeline, a fine-grained node-to-stage mapping is used to achieve evenly distributed memory across the stages. To balance the traffic on different pipelines, both pipelined prefix caching and dynamic subtrie-topipeline remapping are employed. Simulation using real-life data shows that the proposed architecture with 8 pipelines can store a core routing table with over 200K unique routing prefixes using 3.5 MB of memory. It achieves a throughput of up to 3.2 billion packets per second, i.e. 1 Tbps for minimum size (40 bytes) packets.

show abstract

Scalable IP lookup for programmable routers

Cited by 45 publications

References 7 publications

High-Speed Prefix-Preserving IP Address Anonymization for Passive Measurement Systems

High-Speed Prefix-Preserving IP Address Anonymization for Passive Measurement Systems

A Pipelined IP Address Lookup Module for 100 Gbps Line Rates and beyond

Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup

Contact Info

Product

Resources

About