Scalable modeling and wideband measurement techniques for a signal TSV surrounded by multiple ground TSVs for RF/high-speed applications

Lu, Kuan-Chung; Horng, Tzyy‐Sheng; Li, Hsin-Hung; Fan, Kung-Chin; Huang, Tzu-Yuan; Lin, Chun-Hsun

doi:10.1109/ectc.2012.6248961

Cited by 14 publications

(14 citation statements)

References 8 publications

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“…From the concept of parallel-wires electrical model [14] and applying the modified substrate capacitance magnification factor-M [15], the inductance of TSV L TSV and the capacitance of silicon substrate C Si could be wrote as eq.5 and eq.6. Both equations contain the following parameters: h TSV , d TSV , the GSG pitch p TSV , the vacuum permeability  0 , the relative permittivity of silicon substrate  0 and the number of M which is related the number of ground TSV and ranged from eq.1 to eq.2.…”

Section: Modeling Of Through Silicon Viasmentioning

confidence: 99%

Electrical model analysis & measurement of TSV to TSV coupling capacitance

Yang

Fan

et al. 2013

2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

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In order to achieve high density and high performance package, Through Silicon Vias (TSVs) technology had been developed; TSVs provide a short distance and low loss structure between different stack layers. Due to the low TSVs' yield impacting the final product significantly, the suitable test method of TSVs within the process is vital to avoid products with the fault during the mass production. By virtue of the inherent capacitive characteristics, it could be detected the faulty TSVs with little area overhead for the circuit under testing. In this paper, we presented an analysis for electrical model and measurement of TSVs' coupling capacitance by different pitches. Also, we proposed the single-side test architecture and the probe technique for TSV testing. The final modeled and measured results show that this testing technique could be practically applied to the process of TSVs formation.

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Section: Modeling Of Through Silicon Viasmentioning

confidence: 99%

Electrical model analysis & measurement of TSV to TSV coupling capacitance

Yang

Fan

et al. 2013

2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

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“…For bump connection, the TSV is relatively much shorter than wire and therefore provides the better signaling path for memory data access. From [2], the insertion loss can be optimized from different ground pitch and patterns.…”

Section: Introductionmentioning

confidence: 99%

Electrical analysis of low distortion transmission design and stacking TSVs on silicon interposer

Kuo

Wang

2016

2016 International Conference on Electronics Packaging (ICEP)

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In this paper, the performance of GSG co-planar waveguide (CPW) type transmission line on silicon interposer and stacking memories by through-silicon-vias (TSVs) are analyzed. The high conductor loss of fine lines will cause the impedance varying with frequency and make the reflection loss minor. Furthermore the flat attenuation of such fine line will result in low distortion waveforms and have better jitter performance compared to conventional wire-bonded memory stacking and PCB routing design. Both frequency and time domain are discussed and analyzed.

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“…However, before applying the TSV technologies to 3DIC packaging, the fundamental electrical properties of TSV should be characterized to evaluate the signal quality for the stacked dies. Interested in the electrical model and properties especially for RF/high-speed applications [1][2][3][4][5][6] has been surging these years.…”

Section: Introductionmentioning

confidence: 99%

Electrical model analysis of RF/high-speed performance for different designed TSV patterns by wideband double side measurement techniques

Lin

Liu

Huang

et al. 2012

2012 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

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Within this paper, four different pitches of Through Silicon Via (TSV) of single-ended ground-signal-ground (GSG) signaling configuration with redistribution layer (RDL) and testing pad that ranging from 20 μm, 50 μm, 100 μm to 200 μm has been made to verify the Radio-Frequency (RF) characteristic of TSV. We propose the modified RF electrical equivalent model of TSV with its' deembed patterns. With the help of the direct double side probing system, wide band measurement of S-parameters of up to 40 GHz and eye-diagrams of 40 Gb/s signal are made to validate the modeled results.

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Scalable modeling and wideband measurement techniques for a signal TSV surrounded by multiple ground TSVs for RF/high-speed applications

Cited by 14 publications

References 8 publications

Electrical model analysis & measurement of TSV to TSV coupling capacitance

Electrical model analysis & measurement of TSV to TSV coupling capacitance

Electrical analysis of low distortion transmission design and stacking TSVs on silicon interposer

Electrical model analysis of RF/high-speed performance for different designed TSV patterns by wideband double side measurement techniques

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Scalable modeling and wideband measurement techniques for a signal TSV surrounded by multiple ground TSVs for RF/high-speed applications

Cited by 14 publications

References 8 publications

Electrical model analysis &amp; measurement of TSV to TSV coupling capacitance

Electrical model analysis &amp; measurement of TSV to TSV coupling capacitance

Electrical analysis of low distortion transmission design and stacking TSVs on silicon interposer

Electrical model analysis of RF/high-speed performance for different designed TSV patterns by wideband double side measurement techniques

Contact Info

Product

Resources

About

Electrical model analysis & measurement of TSV to TSV coupling capacitance

Electrical model analysis & measurement of TSV to TSV coupling capacitance