Scalable shared-buffering ATM switch with a versatile searchable queue

Yamanaka, Hidetoshi; Saitō, Hideo; Kondoh, H.; Sasaki, Y.; Yamada, Hiroyuki; Tsuzuki, M.; Nishio, S.; Notani, H.; Iwabu, A.; Ishiwaki, M.; Kohama, S.; Matsuda, Yoshihisa; Oshima, Koichiro

doi:10.1109/49.594840

Cited by 28 publications

(16 citation statements)

References 32 publications

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“…In this case, B(3,2), with R = 5, is the second, B(3,1), with a queue length of 4, is the buffer with the longest queue, and is given the fourth priority. There are three buffers with the next longest queue, L = 3, namely, B(1,1), B(2,2), and B (3,3). Their orders are determined in accordance with the random values R assigned beforehand to the buffers, namely, as B (3,3), B(1,1), B(2,2).…”

Section: The Proposed Schemementioning

confidence: 99%

“…Then, HoL cells are switched from B(1,2), B(2,3), and B(3,1). Consider B (3,2). If a cell arrives at the next time slot, that cell is discarded due to buffer overflow.…”

Section: The Conventional Schemementioning

confidence: 99%

“…ATM switches which are used in transferring data are divided into the shared buffer type [2,3], the output-buffered type [4], and the input-buffered type [1,[5][6][7][8][9][10], according to the location of the buffer. In the shared buffer type switch, all buffer memory is shared, which gives the advantage that less memory capacity is required for the buffer.…”

Section: Introductionmentioning

confidence: 99%

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A scheduling scheme for variable‐length packets in an input‐buffered ATM switch with priority of active buffer

Nakaki

Okazaki

Sakamoto

et al. 2003

Electron. Comm. Jpn. Pt. I

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SUMMARYIn ATM (asynchronous transfer mode) we propose a VOQ (virtual output queuing) switch in which the same number of buffers as the number of output ports are provided in each input port, serving as an input-buffered switch to avoid HoL (head of line) blocking. In addition, in order to handle the recent increase of IP traffic, the IP-PIM (IP-parallel iterative matching) scheme is proposed as the scheduling scheme for the VOQ switch using variablelength packets. However, the IP-PIM scheme has the problem that the queue lengths in other buffers are increased, since cells belonging to the same packet are always handled continuously, which degrades the packet loss probability. Consequently, this paper proposes a scheduling scheme with active buffer priority in which the buffer receiving the cells belonging to the packet under consideration is defined as the active buffer and is given priority. In the proposed scheme, the queue length is reduced by giving the priority to the active buffer, and efficient switching is realized. The packet loss probability and the average packet delay are evaluated by computer simulation. It is found that the proposed scheme can greatly improve the packet loss probability compared to the conventional scheme, with degradation of the average packet delay by approximately 20 slots. It is also shown that a satisfactory loss probability is realized even if the buffer size is small, and that good expandability with regard to the switch size is achieved.

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Section: The Proposed Schemementioning

confidence: 99%

“…Then, HoL cells are switched from B(1,2), B(2,3), and B(3,1). Consider B (3,2). If a cell arrives at the next time slot, that cell is discarded due to buffer overflow.…”

Section: The Conventional Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A scheduling scheme for variable‐length packets in an input‐buffered ATM switch with priority of active buffer

Nakaki

Okazaki

Sakamoto

et al. 2003

Electron. Comm. Jpn. Pt. I

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show abstract

“…The scalability of a shared-memory switch has been addressed by the sliding-window (SW) packet switch [1] [7] and the shared-multibuffer packet switch [8] [9] designs. These packet switches make use of an array of parallel memory modules (instead of a single, large memory) to reduce the required memory bandwidth and enable the switching system to perform parallel-write and parallel-read operations.…”

Section: Introductionmentioning

confidence: 99%

Buffer Management in the Sliding-Window (SW) Packet Switch for Priority Switching

Muñoz¹,

Kumar²

2014

IJCNS

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Switch and router architectures employing a shared buffer are known to provide high throughput, low delay, and high memory utilization. Superior performance of a shared-memory switch compared to switches employing other buffer strategies can be achieved by carefully implementing a buffer-management scheme. A buffer-sharing policy should allow all of the output interfaces to have fair and robust access to buffer resources. The sliding-window (SW) packet switch is a novel architecture that uses an array of parallel memory modules that are logically shared by all input and output lines to store and process data packets. The innovative aspects of the SW architecture are the approach to accomplishing parallel operation and the simplicity of the control functions. The implementation of a buffer-management scheme in a SW packet switch is dependent on how the buffer space is organized into output queues. This paper presents an efficient SW buffermanagement scheme that regulates the sharing of the buffer space. We compare the proposed scheme with previous work under bursty traffic conditions. Also, we explain how the proposed buffer-management scheme can provide quality-of-service (QoS) to different traffic classes.

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“…It uses an M N, M N , switch as a basic unit where M;N are the numbers of input and output ports respectively. Scalability can be achieved by using a funnel structure [10] if needed. Shared memory blocks are used to solve the access rate problem and are described hereafter, while a sorting queue addresses the buffer management unit complexity problem.…”

Section: Switch Architecturementioning

confidence: 99%

A VLSI switch architecture for broadband satellite networks

Wassal

Hasan²

1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)

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In this paper, an ATM switch architecture is proposed for satellite on-board processing. The switch is based on a shared memory architecture for the switching fabric and a circular sorting queue for the buffer management unit. The design is constrained by both the network performance requirements and the limited payload of the satellite in terms of mass, area and power. A low-power ASIC implementation of the sorting queue that can support an aggregate traffic rate up to 21.2 Gbps is also presented.

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Scalable shared-buffering ATM switch with a versatile searchable queue

Cited by 28 publications

References 32 publications

A scheduling scheme for variable‐length packets in an input‐buffered ATM switch with priority of active buffer

A scheduling scheme for variable‐length packets in an input‐buffered ATM switch with priority of active buffer

Buffer Management in the Sliding-Window (SW) Packet Switch for Priority Switching

A VLSI switch architecture for broadband satellite networks

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