Scalable Two-Transistor Memory (STTM)

Yi, Ji Soo; Kim, W.S.; Song, S.; Khang, Yoonho; Kim, H.-J.; Choi, J.H.; Lim, Hyon-Chol; Lee, N.I.; Fujihara, K.; Kang, Hyung-Geun; Moon, Jiwon; Lee, M.Y.

doi:10.1109/iedm.2001.979632

Cited by 4 publications

(3 citation statements)

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“…In the paper of Yi et al (2001), they present experimental results of STTM. The operation principle and the cell structure of STTM are originally proposed by Nakazato (Nakazato et al, 2000) with the name called PLEDM (Nakazato et al, 1997(Nakazato et al, , 1999(Nakazato et al, , 2000Mizuta et al, 1998).…”

Section: Scalable Two-transistor Memorymentioning

confidence: 98%

“…In the work of Yi et al (2001), they have fabricated and successfully demonstrated the memory cell operation of the STTM for the first time. Furthermore, they designed architecture for the high-density STTM cell-array with a unit cell size of 4F 2 and a process scheme to fabricate it, where F is the minimum feature size.…”

Section: Scalable Two-transistor Memorymentioning

confidence: 98%

“…Nakazato et al (2000) have proposed the use of multiple tunnel junction (MTJ) for the vertical transistor for better data retention and higher speed. Figure 7 shows the cell structure and the operation principle of the STTM with MTJ (Yi et al, 2001).…”

Section: Scalable Two-transistor Memorymentioning

confidence: 99%

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Future prospects of DRAM: emerging alternatives

Choi

Latifi

2012

IJHPSA

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DRAM has been the dominant memory for today's computing memory systems due to its high data rate up to 1,866 Mbps. Researchers and developers of DRAM have been striving to improve the performance in terms of higher speed and higher density with lower bit cost. The conventional method of reducing the cost is to scale down. However, scaling-down is becoming a very difficult process because the scale has already reached a 20 nm node which has been recently developed by Samsung. As it becomes difficult to scale down, it becomes harder to have a higher density and yield, and of course, the cost cannot be reduced. Therefore, various memories have been studied and developed as potential candidates for the next generation DRAM. In this paper, we investigate the technical limitations that conventional DRAM needs to overcome, especially in terms of scaling-down. Then, we discuss the emerging memories that can be used as alternatives to DRAM and we point out what advantages they have.

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