Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems

Abstract

A novel high throughput and scalable unified architecture for the computation of the transform operations in video codecs for advanced standards is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute all the two-dimensional 4 x 4 and 2 x 2 transforms of the H.264/AVC standard. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-5 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area relatively higher than other similar recently published designs targeting the H.264/AVC standard. Such results also showed that, when integrated in a multi-core embedded system, this architecture provides speedup factors of about 120x concerning pure software implementations of the transform algorithms, therefore allowing the computation, in real-time, of all the above mentioned transforms for Ultra High Definition Video (UHDV) sequences (4,320 x 7,680 @ 30 fps).

A Systematic Hardware Sharing Method for Unified Architecture Design of H.264 Transforms

“…In recent years, some transform architectures for H.264 encoder/decoder that reduce the hardware cost have been proposed. In general, for low cost multiple transforms of video codecs, hardware sharing is the most suitable technique [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. In [8][9][10][11][12][13], all of the 4 × 4 transforms are realized as a shared architecture.…”

“…In [8][9][10][11][12][13], all of the 4 × 4 transforms are realized as a shared architecture. In [14], 2D 4 × 4 and 2 × 2 transforms are implemented in a FPGA and integrated in a multicore embedded system. In [15,16], pipeline shared architectures for the 8 × 8 forward/inverse integer transform are demonstrated.…”