Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

Veloso, A.; Jourdain, Anne; Radisic, Dunja; Chen, Rongmei; Arutchelvan, Goutham; O’Sullivan, Barry; Arimura, Hiroaki; Stucchi, M.; Keersgieter, A. De; Hosseini, Motaharesadat; Hopf, T.; D’havé, Koen; Wang, S.; Dupuy, Emmanuel; Mannaert, G.; Vandersmissen, K.; Iacovo, Serena; Marien, Philip; Choudhury, S.; Schleicher, F.; Sebaai, Farid; Oniki, Yusuke; Zhou, Xiuju; Gupta, Anshul; Schram, T.; Briggs, B.; Lorant, Christophe; Rosseel, Erik; Hikavyy, Andriy; Loo, Roger; Geypen, J.; Batuk, D.; Martinez, G.T.; Soulié, Jean-Philippe; Devriendt, K.; Chan, Boon Teik; Demuynck, S.; Hiblot, Gaspard; Plas, G. Van der; Ryckaert, Julien; Beyer, Gerald; Litta, Eugenio Dentoni; Beyne, Eric; Horiguchi, N.

doi:10.1109/vlsitechnologyandcir46769.2022.9830177

Cited by 6 publications

(2 citation statements)

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“…The VSS interconnect thus must be placed at the frontside BEOL in A3 CFET SRAM. [15][16], and nTSV is assumed in this work. Regarding the insufficient space at the backside BEOL and frontside MINT layer, the VSS is therefore placed on the frontside M1 layer directly connected to the top PD device by a supervia.…”

Section: E Interconnect Challenge and Solutionmentioning

confidence: 99%

“…Note that the layout designs (Fig.3, 4, 7, 8) work for both Fin-on-Fin and NS-on-NS CFET SRAM by replacing the NS with Fin. In A3 design, VDD as BSM layer can be connected by either BPR or nanoscale through-silicon via (nTSV)[15][16], and nTSV is assumed in this work. Regarding the insufficient space at the backside BEOL and frontside MINT layer, the VSS is therefore placed on the frontside M1 layer directly connected to the top PD device by a supervia.…”

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confidence: 99%

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CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

Liu

Salahuddin

Chan

et al. 2023

IEEE Trans. Electron Devices

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This paper explores and evaluates 6-transistor static random-access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Åm-compatible (A5) and 3-Åm-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scaling due to stacked devices as compared to 14-Åmcompatible (A14) nanosheet technology and 10-Åm-compatible (A10) forksheet technology counterparts, respectively. Dielectric isolation wall (DIW) between gates is introduced in A3 CFET SRAM as a scaling booster. Replacement of gate-cuts with DIW results in up to 17% bitcell area scaling in A3 as compared to A5 CFET SRAM. Aggressive area scaling however introduces routing complexity and limits the node-to-node power and performance gain. The interconnect design guidelines are provided to overcome these challenges for power, performance, and area (PPA) enhancements of high-density (HD) SRAM.

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Section: E Interconnect Challenge and Solutionmentioning

confidence: 99%

mentioning

confidence: 99%

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

Liu

Salahuddin

Chan

et al. 2023

IEEE Trans. Electron Devices

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Inkjet-printed electrical interconnects for high resolution integrated circuit diagnostics

Jacobs

2023

Commun Eng

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As semiconductors continue to shrink in size and become more three-dimensional in shape, the size of defects that can induce a failure also reduces, pushing the need for better fault isolation. The resolving capability of microscopes used in failure analysis (FA) is frequently limited by how close the microscope can be brought to the circuit under test. Accessibility is often restricted by the presence of probe needles or wire bonds that are needed to power up the device during the measurement. Here, I describe a robust, rapid and cost-effective method to overcome the contacting bottleneck by re-routing the probe pads with a low-profile redistribution layer, realized by conductive inkjet printing. I demonstrate that the method enables analytical FA with high spatial resolution on a backside power delivery network structure in combination with the optical beam induced resistance change (OBIRCH) technique. Electrical and structural characterization of the printing process are also reported.

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