Scaling Beyond 7nm Node: An Overview of Gate-All-Around FETs

Hu, Wei; Li, Feng

doi:10.1109/isne48910.2021.9493305

Cited by 12 publications

(8 citation statements)

References 35 publications

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“…The lateral and vertical orientations of GAAFETs in the form of NW or NS show exhibit potential scalability in the sub-10nm regime. Stacked NWGAAFETs with increased pitch can be a good choice for obtaining lower DIBL, controlled SCEs, near-ideal SS and considerable magnitude of ON-current [33]. At 7 nm and 5 nm nodes, gate bias V GS = 0.65 V yields I ON = 16.8 μA and 26 μA and I OFF = 3.5 nA (per fin) for a 2-fin stacked NWGAA [33].…”

Section: Gaafetsmentioning

confidence: 99%

“…Stacked NWGAAFETs with increased pitch can be a good choice for obtaining lower DIBL, controlled SCEs, near-ideal SS and considerable magnitude of ON-current [33]. At 7 nm and 5 nm nodes, gate bias V GS = 0.65 V yields I ON = 16.8 μA and 26 μA and I OFF = 3.5 nA (per fin) for a 2-fin stacked NWGAA [33]. The DIBL for lateral NWGAAFET was reported to be 45 mV/V, 31.4 mV/V, 122 mV/V and 105 mV/V with gate lengths of 10 nm,15 nm and 25 nm respectively [33,34].…”

Section: Gaafetsmentioning

confidence: 99%

“…At 7 nm and 5 nm nodes, gate bias V GS = 0.65 V yields I ON = 16.8 μA and 26 μA and I OFF = 3.5 nA (per fin) for a 2-fin stacked NWGAA [33]. The DIBL for lateral NWGAAFET was reported to be 45 mV/V, 31.4 mV/V, 122 mV/V and 105 mV/V with gate lengths of 10 nm,15 nm and 25 nm respectively [33,34]. NSGAA exhibit a better current drive as compared to FinFETs as the effective width is more.…”

Section: Gaafetsmentioning

confidence: 99%

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More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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The progress in IC miniaturization dictated by Moore’s Law has taken a leap from mere circuit integration to IoT enabled System-on-Chip (SoC) deployments. Such systems are connoted by contemporary advancements in the semiconductor industry roadmaps namely, ‘More-Moore’ and ‘More-than-Moore’ (MtM). For meaningful integration of digital and non-digital blocks, a power performance tradeoff is essential for maximum and fruitful utilization of the silicon area. Using the techniques under the MtM nomenclature allows the use of unconventional steep slope devices like Tunneling FETs, Negative Capacitance (NC) FETs, Gate-all-around FETs (GAA) and FinFETs etc., which can exhibit reasonable performance with lower supply voltages. Following the Device Technology Co-optimization (DTCO) and System Technology Co optimization (STCO) the advanced 3D heterogenous integration technologies allow sensors, analog/mixed signal and passive components to be assimilated within the same package as the CMOS blocks. Appropriate device engineering techniques like multi-gate architectures, vertical stacking transistors, compound semiconductors and alternate carrier transport phenomena are required to improve the current drive and scaling performance of advanced CMOS devices. CMOS based codesign is essential to realize new topologies for energy economical computation, sensing and information processing as the beyond CMOS steep slope devices are independently incapable of replacing conventional bulk CMOS devices. This article presents a detailed qualitative review of the various aspects of MtM beyond CMOS steep slope switches and their prospective integration technologies. For system level integration, various aspects of device performance and optimizations, related device-circuit interactions, dielectric technologies at the advance nanometer nodes have been probed into. Additionally, novel circuit topologies, synthesis algorithms and processor level performance evaluation using steep slope switches have been investigated. An exclusive compact overview for contemporary insights into integrated device-system development methodology and its performance evaluation is presented.

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Section: Gaafetsmentioning

confidence: 99%

Section: Gaafetsmentioning

confidence: 99%

Section: Gaafetsmentioning

confidence: 99%

See 1 more Smart Citation

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

View full text Add to dashboard Cite

show abstract

“…The proposed NS CFET technology was realized by stacking a p-type nanosheet gate-all-around (GAA) FET on top of an n-type GAA FET (figures 6(b) and (c)). In comparison to the FinFET, which is the state-of-theart technology, the GAA structure enables electrical shielding between stacked transistors, providing a more efficient scheme for vertical stacking [83]. The inverter VTC of both the NS CMOS and CFET circuits are shown in figure 6(d).…”

Section: Nanosheet Complementary Fetsmentioning

confidence: 99%

Vertical integration: a key concept for future flexible and printed electronics

Han¹,

Kim²,

Jung³

2022

Flex. Print. Electron.

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This review aims at introducing a vertical integration approach as a promising new driver of field-effect transistor circuits and systems, which can overcome limitations of flexible and printed electronics. A large portion of this article is dedicated to systematic categorization and illustration of important and recent demonstrations of vertically integrated circuit building blocks incorporating organic materials, metal-oxide semiconductors, nanotubes, and nanosheets. Key features of each of these materials platforms and their fabrication issues are also broadly discussed. Then, common technical requirements for high-performance devices and circuits are critically evaluated in view of the specific geometrical and theoretical aspects of vertically connected complementary digital logic inverters. Prominent technological opportunities and challenges for the vertical and three-dimensional transistor integration are finally addressed to further motivate active multidisciplinary research on related materials, devices, and systems.

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“…The unique structure of the GAA NWFET in which the channel is surrounded by gate all around it -thus the name "Gate-All-Around" -provides the transistor with high surface-to-volume ratio [3] and this con guration also gives a better gate controllability over the channel as compared to other advanced MOSFET con gurations such as the FinFET. In terms of scalability, the nanosheet dimensions are easier to be sized [4] to meet speci c performance requirements. Emerging technologies as these has enabled the manufacturing of nanoscale devices with low power consumption and high switching speed.…”

Section: Introductionmentioning

confidence: 99%

Process variations and short channel effects analysis in gate-all-around nanowire field-effect transistor using a statistical Taguchi-Pareto ANOVA framework

Yau

Hatta

Wahab

et al. 2022

Preprint

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Gate-all-around nanowire field-effect transistor (GAA NWFET) is a viable alternative to reduce short channel effects. A 3D model of the GAA NWFET was explored by studying the effect of process parameters such as nanowire materials, gate oxide materials and high-κ coverage angles on vital transistor performance metrices specifically threshold voltage, leakage current, current ratio, subthreshold swing (SS) and drain induce barrier lowering (DIBL). It has been observed that the nanowire material of InP provides the lowest threshold voltage and highest drive current. Gate oxide material of HfO2 showed improved leakage current by 88.39%, current ratio by 1439.63%, SS by 24.16% and DIBL by 13.11% relative to the conventional NWFET with SiO2 gate oxide. Moreover, as the high-κ dielectric (HfO2) covers the gate oxide over the channel region, the gate electrostatic control over the channel region increases, thus reducing SS to an ideal value. An exhaustive Taguchi Method with Conceptual Signal-To-Noise Ratio Approach and Pareto Analysis of Variance optimization was conducted to determine the optimal design for high current ratio and low threshold voltage. This work inherently provides a framework in designing an optimized GAA NWFET by considering the device’s highest to lowest domineering design factors in affecting its performance matrices.

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Scaling Beyond 7nm Node: An Overview of Gate-All-Around FETs

Cited by 12 publications

References 35 publications

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Vertical integration: a key concept for future flexible and printed electronics

Process variations and short channel effects analysis in gate-all-around nanowire field-effect transistor using a statistical Taguchi-Pareto ANOVA framework

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