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Silicon carbide integrated circuits have been demonstrated to operate at high temperatures, such as ~460ºC at the Venus' surface, for two months and for over a year at 500ºC. At these high temperatures, the SiC integrated circuits and sensors need to be packaged in quite different ways than those below 300ºC. In addition, to integrate more devices into the limited footprint of the high-temperature circuit board, 3D packaging is a notable advantage. In this work, 3D stacking of SiC chips using a gold wirebonding interconnect is investigated. The gold bonding wire is used due to its mechanical robustness and chemical inertness at high temperatures. Triple-stacked SiC chips are bonded to each other and to the gold contact pads on the alumina substrate with screen-printed gold pastes. The mechanical die shear test, wire pull tests, and interconnect electrical resistance tests are executed and analyzed before and after the 3D SiC chip packages are subject to a 600ºC thermal aging process in air for up to ten days. This 3D SiC chip packaging has promise for longduration high temperatures (up to 600ºC) applications and may be potentially of use for applications such as Venus's surface sensing and telemetry.

Silicon photonics is a disruptive semiconductor technology that taps into the extraordinary properties of light while taking full advantage of the already matured CMOS processes developed in the semiconductor industry. However, just like electronic industry in the 1970s, currently, Silicon Photonics is in its infancy. The fundamental building blocks of silicon photonics such as waveguides, lasers, modulators, etc. are yet to be fully optimized for low-cost-mass-manufacturing. In this paper, the current state-of-the-art related to developing and optimizing these aforementioned key components will be presented. The challenges of process integration regarding Silicon photonics will also be discussed.

The Moore's law is approaching to an end at today's 14 nm technology and System in Package (SiP) is a promising solution for achieving denser electronics like mobile phones with small form factors. System in package is bringing together multiple ICs of various functionality stacked in 3D fashion. A fully functional system consisting of passive elements like resistor, capacitor, inductors, electromechanical elements, antenna, and ICs like sensors, can be integrated into a single package. To meet the requirements of the end product, system design characterization becomes very important for overall success in the development of system in package. Failure analysis and testing of the end product helps improve the product yield which is a point of concern for industries while designing system in package. But system in package has proven to be a viable solution for reduction in total cost and minimize time-to-market. Hence, system in package will continue to thrive and grow into mainstream technology despite of challenges faced during the development and production phase. In this paper, summary of system in package is presented with the perspective of reviewing the research carried out to overcome the challenges, cost issues, compatibility of different functional dice, quality and reliability issues. This paper discusses the recent technological development of system in package modules and the limitations faced at various system levels while bringing multiple chips together to achieve fully functional package. This paper focuses on bridging the gap between the system integration by reviewing the research progress in the 3D IC and packaging using system in package. Some of the applications like portable electronics, automotive and wearable electronics, where the significance of system in package is more relevant are reviewed in this paper. The core challenges like thermal management, flip chip or wire bond interconnect that arise due to integration of different components and packages like package on package, package in package in the system in package are also discussed.