Scaling CMOS photonics transceivers beyond 100 Gb/s

Mekis, Attila; Abdalla, Sherif; Dobbelaere, Peter M. De; Foltz, D.; Gloeckner, S.; Hovey, S.; Jackson, S.A.; Liang, Yi; Mack, M.; Masini, G.; Novais, Rafaela; Peterson, Mark; Pinguet, Thierry; Sahni, S.; Schramm, J.; Sharp, M.; Song, Donghui; Welch, B.; Yokoyama, K.; Yu, S.

doi:10.1117/12.911581

Cited by 20 publications

(10 citation statements)

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“…In 2010, Luxtera demonstrated a 40-Gb/s optoelectronic transceiver, based on a single III/V continuous-waveform (cw) laser enclosed in an optical micropackage (including a lens and isolator) that was flip-chipped onto the underlying silicon die and optically coupled to the photonic chip via grating couplers [196]. Further evolution of this device led to the demonstration of the first 100-Gb/s optical transceiver, where a micropackaged distributed feedback (DFB) laser was epoxy-bonded onto the chip [197].…”

Section: I N T E G R At E D L I G H T S O U R C E Smentioning

confidence: 99%

The Emergence of Silicon Photonics as a Flexible Technology Platform

et al. 2018

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| In this paper, we present a brief history of silicon photonics from the early research papers in the late 1980s and early 1990s, to the potentially revolutionary technology that exists today. Given that other papers in this special issue give detailed reviews of key aspects of the technology, this paper will concentrate on the key technological milestones that were crucial in demonstrating the capability of silicon photonics as both a successful technical platform, as well as indicating the potential for commercial success. The paper encompasses discussion of the key technology areas of passive devices, modulators, detectors, light sources, and system integration.In so doing, the paper will also serve as an introduction to the other papers within this special issue.

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Section: I N T E G R At E D L I G H T S O U R C E Smentioning

confidence: 99%

The Emergence of Silicon Photonics as a Flexible Technology Platform

et al. 2018

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“…Dan-Xia Xu, Jens H. Schmid, Graham T. Reed, Goran Z. Mashanovich, David J. Thomson, Milos Nedeljkovic, Xia Chen, Dries Van Thourhout, Shahram Keyvaninia, Shankar K. Selvaraja SOI with 300-310 nm thick silicon, which was chosen to accommodate low loss compact passive devices and for a bulk-like transistor process [35,36]. Silicon photonics development at Oracle is also based on this platform [37].…”

Section: Silicon Photonic Integration Platform -mentioning

confidence: 99%

“…With the compact device size and potentially high level of integration enabled by the high index contrast in silicon waveguides, the cost of the PICs is largely determined by the fabrication facilities required, the complexity of the processes and the yield of all fabrication steps [41]. Due to insufficient control in the waveguide dimensions using current fabrication technologies that result in variability in the optical phase within devices, wavelength dispersive components are generally biased to the desired operating point by thermal tuning or using a p-i-n junction [35,42,43]. Device power consumption is therefore not only determined by the efficiencies of signal modulation and detection, it is also strongly affected, and at times even dominated, by the power necessary for biasing.…”

Section: Overview Of Key Components In An Optical Transceiver Andmentioning

confidence: 99%

Silicon Photonic Integration Platform—Have We Found the Sweet Spot?

Schmid

Reed

et al. 2014

IEEE J. Select. Topics Quantum Electron.

117

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The current trend in silicon photonics towards higher levels of integration as well as the model of using CMOS foundries for fabrication are leading to a need for standardization of substrate parameters and fabrication processes. In particular, for several established research and development foundries that grant general access, silicon-oninsulator wafers with a silicon thickness of 220 nm have become the standard substrate for which devices and circuits have to be designed. In this study we investigate the role of silicon device layer thickness in design optimization of various components that need to be integrated in a typical optical transceiver, including both passive ones for routing, wavelength selection, and light coupling as well as active ones such as monolithic modulators and on-chip lasers produced by hybrid integration. We find that in all devices considered there is an advantage in using a silicon thickness larger than 220 nm, either for improved performance or for simplified fabrication processes and relaxed tolerances.

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“…This will cause certain obstacles to measurement because the best position of fiber needs to be carefully tuned using a high-precision fiber-alignment system. Secondly, it is very difficult to package the tilted fiber except by using angle-polishing [8], [9]. Therefore, a vertical coupler without much decrease in efficiency will be a demand.…”

Section: Introductionmentioning

confidence: 99%

CMOS-Compatible Vertical Grating Coupler With Quasi Mach–Zehnder Characteristics

Zhang

Huang

Cheng

et al. 2013

IEEE Photon. Technol. Lett.

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A vertical grating coupler on silicon-on-insulator substrates has been designed and demonstrated. The light from a vertical fiber can be coupled in and split equally into two arms with the fiber placed in the grating center. An optical combiner is used to collect the transmission from the two arms. The measured peak coupling efficiency is 37%. Our device can also function like a Mach-Zehnder interferometer. In a device with an arm difference of 30 µm, the normalized transmission spectra of 20-nm free spectral range and more than 12-dB extinction ratio at 1567 nm are obtained.

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Scaling CMOS photonics transceivers beyond 100 Gb/s

Cited by 20 publications

References 0 publications

The Emergence of Silicon Photonics as a Flexible Technology Platform

The Emergence of Silicon Photonics as a Flexible Technology Platform

Silicon Photonic Integration Platform—Have We Found the Sweet Spot?

CMOS-Compatible Vertical Grating Coupler With Quasi Mach–Zehnder Characteristics

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