Scaling considerations for sub-90 nm split-gate flash memory cells

Saha, Samar K.

doi:10.1049/iet-cds:20070126

Cited by 18 publications

(3 citation statements)

References 13 publications

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“…As a result, the modelling attempt of ∆I D of MOSFET was derived in [12] where the nanome- Final manuscript received on April 13, 2020. 1 The author is with Graduated School of IT and Faculty of Engineering, Siam University, Bangkok, Thailand., E-mail: rawid b@yahoo.com 2 The author is with School of IT, Mae Fah Luang University, Chiangrai, Thailand., E-mail: roungsan.cha@mfu.ac.th DOI: 10.37936/ecti-cit.2020142.123097…”

Section: Introductionmentioning

confidence: 99%

The Completed Probabilistic Modelling of Nanometer MIFGMOSFET

Banchuin

Chaisrichaoren

2020

ECTI-CIT

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A completed model of the probabilistic distribution of the drain current’s random variation of the nanometer multiple input floating gate MOSFET (MIFGMOSFET) is proposed in this work. The modelling process has taken the dominant physical level causes of the drain current’s variations into account. Unlike its predecessor, the proposed model considers both N-type and P-type nanometer MIFGMOSFET. Moreover, the formerly neglected parasitic coupling capacitances have also been taken into account. The obtained modelling results, which are based on the derived drain current’s equations of nanometer MIFGMOSFET, are very accurate. They can predict the probabilistic distributions of the candidate N-type and P-type nanometer MIFGMOSFETs obtained by using Monte-Carlo simulations with 99% confidence and higher accuracy than that of the previous work. We also perform a comparative robustness study of the nanometer MIFGMOSFET of both types and demonstrate various interesting applications of our modelling results

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Section: Introductionmentioning

confidence: 99%

The Completed Probabilistic Modelling of Nanometer MIFGMOSFET

Banchuin

Chaisrichaoren

2020

ECTI-CIT

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“…However, the advantages of SOI technology are not limited to the area of speed and power, it also has advantages in term of the ability to withstand high temperature and handle high voltage. A thin layer about tens of nanometer active silicon is placed on top of a thick layer of insulator such as silicon dioxide (SiO 2 ) or sometimes referred as Buried Oxide (BOX) (Sugii et al, 2008;Colinge, 2008;Kilchytska et al, 2011;Kranti et al, 2010) and this dielectric isolation of silicon reduces the parasitic or internal junction capacitance on components and thus improves device performance by a huge percentage (Lee et al, 1998;Saha, 2009;Saha, 2008).…”

Section: Introductionmentioning

confidence: 99%

A Comparative Study on SOI MOSFETs for Low Power Applications

Rosli

Hafizi

Daud

et al. 2013

RJASET

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Silicon on Insulator (SOI) technology has become one of the most promising technologies in semiconductor fabrication industry for its numerous advantages. This study presents merits and demerits of different SOIs presented in literatures and a comparative study is done based on several design and performance issues for low power applications. From the study it is found that Fully Depleted SOI MOSFET (FDSOI) technology is preferred due to its thin size, reduced leakage current and improved power consumption characteristics etc. compared to those of PDSOI and bulk silicon technology.

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“…Similarly, program efficiency in a split-gate flash with a p-floating gate could be higher as the source-side injection was used [8] due to the change of work function in floating gate poly. In addition, a coupling-gate (CG) above the FG was added to a split-gate cell to reduce the common source voltage, and thus the high endurance [9][10][11].…”

Section: Introductionmentioning

confidence: 99%