Scaling Energy Per Operation via an Asynchronous Pipeline

Marr, Bo; Degnan, Brian; Hasler, P.; Anderson, David V.

doi:10.1109/tvlsi.2011.2178126

Cited by 68 publications

(32 citation statements)

References 20 publications

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“…Although energy efficiency in digital computation improved dramatically with scaling down of transistors, the issue of threshold voltage (V T0 ) mismatch between transistors has effectively brought energy efficiency of commercial digital ICs to a standstill [9,10]. This digital processing energy efficiency wall calls out for new solutions to meet the appetite of the next generation of computing.…”

Section: Why Analog Numerical Analysis?mentioning

confidence: 99%

“…As IC processes shrink to smaller transistor dimensions (e.g., 40 nm and below) and power supplies, these issues become almost insurmountable for analog design. Digital computation being limited by V T0 mismatch [9] makes the situation for analog computation look less likely. Figure 5 shows the precision of storage and simple element SNR versus expected cost, showing that analog has advantages for lower precision and showing digital has advantages for higher precision after a particular crossover point.…”

Section: Digital Strength: Lower Cost Numerical Precisionmentioning

confidence: 99%

“…The energy efficiency wall (introduced in Section 2) for digital computation [9], roughly around 10 MMAC(/s)/mW, is primarily constrained by device-to-device mismatch. Timing accuracy between digital logic gates is essential for reliable digital computation.…”

Section: Multiplication Analog Digitalmentioning

confidence: 99%

“…Just decreasing transistor linewidth, without improving transistor mismatch results in no improvement in energy or power efficiency. For digital systems, this mismatch has not improved with transistor scaling since the 180-nm CMOS node [9]. Further, typical digital cells tend to keep the product of W and L relatively constant with scaling, getting better performance with decreasing L (increasing W/L), but not improving the resulting energy efficiency.…”

Section: Multiplication Analog Digitalmentioning

confidence: 99%

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Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

Hasler

2017

JLPEA

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Abstract:The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer tools to make reasonable choices. Analog numerical analysis concerns computation on physical structures utilizing the real-valued representations of that physical system. This work starts the conversation of analog numerical analysis, including exploring the relevancy and need for this framework. A complexity framework based on computational strengths and weaknesses builds from addressing analog and digital numerical precision, as well as addresses analog and digital error propagation due to computation. The complimentary analog and digital computational techniques enable wider computational capabilities.

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Section: Why Analog Numerical Analysis?mentioning

confidence: 99%

Section: Digital Strength: Lower Cost Numerical Precisionmentioning

confidence: 99%

Section: Multiplication Analog Digitalmentioning

confidence: 99%

Section: Multiplication Analog Digitalmentioning

confidence: 99%

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Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

Hasler

2017

JLPEA

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“…T HE observation of a fundamental power-efficiency wall for digital circuits [1] has encouraged engineers to consider new processing approaches. This challenge has created a renewed interest in techniques such as neuromorphic computation, pioneered in [2], where the natural physics of the subthreshold transistor is used as a computational primitive.…”

Section: Introductionmentioning

confidence: 99%

High-Level Modeling of Analog Computational Elements for Signal Processing Applications

Schlottmann

Hasler

2014

IEEE Trans. VLSI Syst.

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Large-scale field-programmable analog array ICs have made analog and analog-digital signal processing techniques accessible to a much wider community. Given this opportunity, we present a framework for considering analog signal processing (ASP) techniques for low-power systems. The core of this paper is the definition of an analog abstraction methodology and the creation of a library of high-level analog computation blocks. By abstracting the analog design, we ensure that users have a similar experience to what they would expect with digital design, thus empowering system-level engineers to take advantage of ASP concepts. The result of this paper is to pull analog computation toward system-level development, comparable with the trend in digital system design over the last 30 years.Index Terms-Analog signal processing (ASP), fieldprogrammable analog array (FPAA), rapid analog prototyping.

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