Scaling impact on analog performance of sub-100nm MOSFETs for mixed mode applications

Analog circuits in ultra-deep-submicron CMOS

“…With a fixed transistor length, e.g., for voltage gain or accuracy reasons, the transistor's intrinsic speed hardly changes over technology. Combined with the findings in the previous parts of this section, it follows that there is a clear trade-off between gain and speed via transistor length (see also [10]). Circuits in newer CMOS technologies can hence achieve higher bandwidths but at the cost of degraded quasi-dc performance.…”

“…This relation implies that for track-and-hold circuits the maximum hold time for a droop amounting to is (10) Allowing, e.g., 1-mV drop on a sampled-and-held value, the maximum usable hold time is in the millisecond range in 180-nm technologies, which is usually sufficient. However the maximum hold time decreases rapidly with newer technologies, down to a typical value in the low nano second range for 65-nm technologies.…”

Analog design criteria for high-granularity detector readout in the 65 nm CMOS technology

“…Instead, if L scales by the same factor a as the technology node, the intrinsic gain is not degraded by scaling in agreement with the constant field scaling rules [4]. Keeping the intrinsic gain constant with scaling is considered one of the major challenges in the design of high-performance analog circuits in scaled-down technologies [5]. While process details for the investigated technologies are unknown, negligible change in gain with device scaling can be reasonably explained by assuming that less aggressive performance-enhancing techniques are applied to the investigated GP and LP devices as compared to High Performance (HP) transistors that are usually available among the various flavors of a nanoscale technology.…”

On the energy efficiency of analog circuits in nanoscale CMOS technologies

“…As pointed out in [5], keeping the intrinsic gain unchanged across technology nodes is not feasible since it requires increasing the threshold voltage as line widths are scaled down, an increase that in most cases, is not acceptable. Hence the intrinsic gain is reduced for every technology node.…”