Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model

Abstract

In our attempts to scale FETs to the 10 nm length, alternatives to conventional Si CMOS are sought on the grounds that: (1) Si seems to have reached its technological and performance limits and (2) the use of alternative highmobility channel materials will provide the missing performance. With the help of numerical simulations here we establish the reasons why indeed Si seems to have hit an intrinsic performance barrier and whether or not high mobility semiconductors can indeed grant us our wishes. The role of long-and short-range electron-electron interactions are revisited together with a recent analysis of the historical performance trends. The density-of-states (DOS) bottleneck and source starvation issues are also reviewed to see what advantage alternative substrates may bring us. Finally, the well-known 'virtual source model' is analyzed to assess whether it can be used as a quantitative tool to guide us to the 10 nm gate length.

Monte Carlo Study of Ultimate Channel Scaling in Si and In$_{\rm 0.3}$Ga$_{\rm 0.7}$As Bulk MOSFETs

“…The drive current increase in the scaling process is more modest in the InGaAs MOSFETs when compared to the increase in the equivalent Si MOSFETs. This modest increase of the drive current is due to a source starvation caused by a lower density of states in InGaAs 3 when compared to Si [9] and it is reflected in the lower electron density with the scaling along the channel. The increasing intrinsic drive current with the scaling is mostly due to the increase in average electron velocity at the drain side of the scaled transistors [29].…”

“…However, the same scaling process performed on In 0.3 Ga 0.7 As MOSFETs will not significantly increase the electron sheet density in the channel at the drain side of the device despite the increase of the density at the source side. This is caused by a source starvation due to a low density of states occurring in many III-V semiconductors [9] (even at the largest, 25-nm gate length) but the starvation will not be enhanced in the scaling process. Rather opposite, the electron density in the channel starts to increase when the In 0.3 Ga 0.7 As transistors are scaled to a gate length of 5 nm as the density of states is increasing thanks to the additional occupation of upper valleys (L and X) in the source as indicated in Fig.…”

“…The decay of the plasmon oscillations (via Landau damping) will transfer carrier momentum from the channel to the source, thus, making the transfer of momentum from the source to the drain much less efficient. The reduced momentum transfer from the source to the drain will decrease the drain current in the device [9], thus, preventing to achieve ballistic transport regime [10]. In this paper, we investigate the origins of the reduction of momentum transfer from the source to the drain by simulating nanoscaled Si and In 0.3 Ga 0.7 As MOSFETs scaled only in the lateral dimension.…”

Impact of the Coulomb interaction on nano-scale silicon device characteristics

“…It has been pointed out that plasmon excitation in highdoped regions by the channel electrons degrades device performance in very small MOSFETs [2]. This is interpreted as follows.…”

“…This is because the channel is sandwiched with heavily doped source and drain regions in the distance of tens nm and the Coulomb interaction directly affects the transport properties in the channel region [2]. As a result, transport simulations coupled self-consistently with the Poisson N. Sano ( ) Institute of Applied Physics, University of Tsukuba, 1-1-1 Tennoudai, Tsukuba, Ibaraki 305-8573, Japan e-mail: sano@esys.tsukuba.ac.jp equation becomes mandatory for any reliable simulations of device performance of ultra-small MOSFETs [3].…”