Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA

Pandey, Bishwajeet; Pandey, Nisha; Kaur, Amanpreet; Hussain, Dil Muhammad Akbar; Das, Bhagwan; Tomar, Geetam Singh

doi:10.1007/s11277-018-5717-2

Cited by 15 publications

(4 citation statements)

References 17 publications

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“…e weight coefficient is regarded as 18bit integer data, expressed as {1 sign bit + 2 integer bits + 15 decimal places}, or w (3, 15) for short. A large amount of addition and multiplication is involved in the filtering calculation process [33]. With a fixed finite word length, if two fixed-point numbers of N bits each are added, the result is of N + 1 bit; if they are multiplied with each other, the result is of 2N digits.…”

Section: Deciding the Length Of The Lms Filter System Coefficient W(n)mentioning

confidence: 99%

The On-Chip D-LMS Filter Design Method of Wireless Sensor Node Based on FPGA

Meng

et al. 2020

Shock and Vibration

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In the real-time position technology of underground shallow source, the signal denoising performance of wireless sensor nodes directly determines the location speed and accuracy of underground burst point. Because of the complexity and randomness of the underground medium and the fact that underground explosion is a nonstationary transient process, the problems of low convergence rate and poor steady-state performance of the filter exist when the existing LMS algorithm is used for signal denoising. In light of the above concerns, this paper comes up with a signal denoising algorithm and hardware implementation method based on D-LMS (delay-LMS). Firstly, according to the autocorrelation function characteristic of random signal, using the principle that the autocorrelation function time delay characteristic of narrowband signal such as explosion vibration signal is better than that of wideband random signal such as ground noise, the D-LMS filter algorithm is constructed by introducing the time delay parameter. Secondly, the selection method of key parameters in D-LMS hardware implementation is analyzed. Thirdly, the corresponding hardware circuit is designed by FPGA, and the simulation is carried out. Numerical simulation and experimental verification show that compared with the existing LMS improved algorithm, the D-LMS algorithm proposed in this paper has higher denoising stability and better denoising effect. Compared with the signal postprocessing method based on the host computer, the signal denoising speed of this method is significantly improved. This method will provide a powerful theoretical method to solve the problem of high-precision and fast source positioning and provide technical support for the development of high-speed and real-time source positioning instruments.

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Section: Deciding the Length Of The Lms Filter System Coefficient W(n)mentioning

confidence: 99%

The On-Chip D-LMS Filter Design Method of Wireless Sensor Node Based on FPGA

Meng

et al. 2020

Shock and Vibration

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“…Authors used FPGA for real-time simulation for power converters and electric machines [10]. FIR filter using FPGA [11] for green communication is designed. Authors used Kintex, an ultra-scale FPGA to study the power consumption of FIR filter by changing its IO standards.…”

Section: Related Workmentioning

confidence: 99%

Frequency Scaling Based Power Efficient Current Source Design on FPGA

Kaur,

Kumar,

Gandhi

et al. 2019

IJEAT

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 Abstract: Power deficiency is one of the major problems that the whole world is facing now. This is happening because of the immense increase in the world's population and the global increase of industrialization. So in order to minimize the consumption of power, an energy efficient current source is designed with the help of Field Programmable Gate Array (FPGA). This work gives light on how the power variation takes place in a current source with an increase in frequency value. In this research work, the current source is implemented on 28 nanometers (nm) Airtx-7 FPGA. The work is demonstrated on Xilinx 14.1 ISE simulator. VHSIC Hardware Description Language (VHDL) is used for writing the code of current source. The frequency of current source with Airtx-7 FPGA is increased from 100MHz to 5GHz. It is analyzed that the total power consumption is less as the value of frequency is low. So it is always advisable to operate the device at a lower frequency range in orderto save more energy.

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“…They have used custom, low profile, medium profile and high profile hit the sink. In Pandey, et al (2018), FIR filter is using 5% of IO resource available in ultra-scale FPGA. So, then there is a possibility to implement bigger FIR filter in this ultra-scale FPGA.…”

Section: Literature Surveymentioning

confidence: 99%