Scaling performance of interior-point method on large-scale chip multiprocessor system

Abstract

In this paper we describe parallelization of interior-point method (IPM) aimed at achieving high scalability on large-scale chipmultiprocessors (CMPs). IPM is an important computational technique used to solve optimization problems in many areas of science, engineering and finance. IPM spends most of its computation time in a few sparse linear algebra kernels. While each of these kernels contains a large amount of parallelism, sparse irregular datasets seen in many optimization problems make parallelism difficult to exploit. As a result, most researchers have shown only a relatively low scalability of 4X-12X on medium to large scale parallel machines. This paper proposes and evaluates several algorithmic and hardware features to improve IPM parallel performance on largescale CMPs. Through detailed simulations, we demonstrate how exploring multiple levels of parallelism with hardware support for low overhead task queues and parallel reduction enables IPM to achieve up to 48X parallel speedup on a 64-core CMP.

Enhancing File Transfer Scheduling and Server Utilization in Data Distribution Infrastructures

“…Eleyat and Natvig [16], propose an optimized parallel solver leveraging the special capabilities of a Cell processor. Smelyanskiy et al [17] present an optimization of the interior-point methods for large-scale chip multiprocessor systems. Budiu et al [18] describe an alternative implementation of a distributed branch-and-bound solver.…”

An algorithm for the fast solution of symmetric linear complementarity problems

“…On the other hand, Algorithm 3.1 typically spends only 10% of the time in the PGS phase and 90% in the subspace minimization. Hence it effectively offloads the parallelization task to a direct linear solver that is known to parallelize well [28]. Specifically, our adaptation of pardiso, the Cholesky solver used for the experiments in this paper, yields more than 65% utilization on a 64-core chip multiprocessor simulator (see also Schenk [25] for a scalability study for a moderate number of processors on a coarsely coupled shared memory system).…”

IPM based sparse LP solver on a heterogeneous processor

“…Smelyanskiy et al (2007) used supernode-based blocking without use of amalgamation. Instead, they show, using a cycle accurate simulator, that the hardware support for low overhead task queues proposed by Kumar et al (2007) can be used to accelerate the scheduling of small tasks.…”