Scaling trends for random telegraph noise in deca-nanometer Flash memories

Abstract

We present a thorough investigation of the random telegraph noise scaling trend for both NAND and NOR floating-gate Flash memories, including experimental and physics-based modeling results. The statistical distribution of the random telegraph noise amplitude is computed using conventional 3D TCAD simulations, establishing a direct connection with cell parameters. The analysis results in a simple formula for the random telegraph noise amplitude standard deviation as a function of cell width, length, substrate doping, tunnel oxide thickness and drain bias. All the simulation results are in good agreement with experimental data and are of utmost importance to understand the random telegraph noise instability and to control it in the development of next generation Flash technologies.

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

“…However, similar to FG flash, CTF memories also suffer from reliability issues associated with trap generation in the gate stack during program/erase (P/E) cycling, e.g., reduction in memory window (MW), stress-induced leakage current (SILC)-assisted charge loss, and random telegraph noise [8]- [10]. These issues are further aggravated for multiple-level cell (MLC) operation due to higher P/E biases and also as the distinction between different threshold voltage (V T ) levels becomes finer [11]- [13].…”

Charge-related phenomena and reliability of non-volatile memories

“…4). This parameter depends on dopant carrier concentration, oxide thickness, cell dimensions and STI edge roughness, which could increase threshold voltage fluctuations [19]. RTN impact on device is taken into account as an extra margin in threshold voltage spread.…”

Statistical analysis of random telegraph noise in digital circuits

“…RTN-induced I d variation can be up to 40% in 30×30nm devices [2], and the V th variation can be larger than 70mV for the smallest devices at 22nm technology node [3]. The RTN effect increases superlinearly with the scaling down of the device's size [4]. RTN is also a serious concern in CMOS logic circuits [5].…”