Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Sandhya, C.; Oak, A.B.; Chattar, N.; Ganguly, Udayan; Olsen, C.; Seutter, S.M.; Daté, L.; Hung, R.; Vasi, J.; Mahapatra, S.

doi:10.1109/ted.2010.2048404

Cited by 9 publications

(10 citation statements)

References 35 publications

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“…In reference [14], however, high-energy electrons from the gate electrode and/or the SiN layer were considered to be the origin of endurance degradation. It is also common to believe that anode hole injection caused by high-energy electrons are responsible for endurance degradation [11,32]. In contrast, our results show that high-energy electrons and resultant anode hole injection are not the main cause.…”

Section: Degradation During Program/erase Cyclingcontrasting

confidence: 51%

“…Device degradation during cycling operation (repetitive P/E) is one of the major concerns in the use of MONOS memory [7,[10][11][12][13][14]. Although cycling induced endurance was also the issue in the conventional floating-gate (FG) type non-volatile memory, the mechanism of endurance degradation in the FG memory is relatively simple.…”

Section: Degradation During Program/erase Cyclingmentioning

confidence: 99%

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Charge Trapping and Reliability Properties of MONOS Memory with High-k Blocking Layer

et al. 2011

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Carrier trapping and reliability characteristics during the cycling operation of metal-oxide-nitride-oxide-semiconductor (MONOS) devices with a high-k blocking layer (Al 2 O 3 ) have been studied by measuring the injected charge during programming and erasing (P/E). The evaluated charge centroid during P/E indicates that the traps near the SiN/Al 2 O 3 interface are filled at high electric field, while bulk traps in the SiN layer are also available at low electric field. The degradation of MONOS devices in cycling operation is found to be strongly correlated with injected charge during erasing. It is indispensable to suppress hole injection, as well as lowering the electric field to improve endurance of MONOS devices. The discussion of this paper also extends to the structure of the charge trapping layer to improve both cycling endurance and retention simultaneously. Finally, we report that a high-k blocking layer has significant impact on data readout and programming characteristics through its transient dielectric properties.

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Section: Degradation During Program/erase Cyclingcontrasting

confidence: 51%

Section: Degradation During Program/erase Cyclingmentioning

confidence: 99%

Charge Trapping and Reliability Properties of MONOS Memory with High-k Blocking Layer

et al. 2011

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“…The endurance properties of 10 4 cycles may not be enough for memory operation, but could be improved if we used thicker tunnel oxide layer or SiN-layer optimization, as indicated in previous work [19,20].…”

Section: Resultsmentioning

confidence: 98%

Investigation of Endurance Degradation in a CTF NOR Array Using Charge Pumping Methods

Kim²

2016

Transactions on Electrical and Electronic Materials

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The NOR-type SONOS memory devices used in this study were fabricated using a standard 0.35 μm complementary-metaloxide-semiconductor (CMOS) technology. In these devices, the We investigate the effect of interface states on the endurance of a charge trap flash (CTF) NOR array using charge pumping methods. The endurance test was completed from one cell selected randomly from 128 bit cells, where the memory window value after 10 2 program/erase (P/E) cycles decreased slightly from 2.2 V to 1.7 V. However, the memory window closure abruptly accelerated after 10 3 P/E cycles or more (i.e. 0.97 V or 0.7 V) due to a degraded programming speed. On the other hand, the interface trap density (Nit) gradually increased from 3.13×10 11 cm -2 for the initial state to 4×10 12 cm -2 for 10 2 P/E cycles. Over 10 3 P/E cycles, the Nit increased dramatically from 5.51×10 12 cm -2 for 10 3 P/E cycles to 5.79×10 12 cm -2 for 10 4 P/E cycles due to tunnel oxide damages. These results show good correlation between the interface traps and endurance degradation of CTF devices in actual flash cell arrays. Ho-Myoung An

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“…Since the distance between the CG and the corner region of the active area is shorter in the deep SA-STI case, it is expected that the electric field around the corner region of the active area is enhanced. As the generation of N IT and oxide trapped charges (N OT ) during cycle stress is related to the magnitude of electric field, [20][21][22][23][24][25][26][27][28][29][30][31] lower endurance characteristics are observed in the device with large SA-STI depth.…”

Section: Resultsmentioning

confidence: 99%

Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths

Yan

Chen

Lee

et al. 2013

Jpn. J. Appl. Phys.

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The program efficiency and endurance characteristics of sub-50 nm NAND flash devices with various self-aligned shallow trench isolation (SA-STI) depths are investigated. Although a large SA-STI depth improves the neighboring floating gate coupling issue and gate coupling ratio, a low program efficiency is also introduced. In addition, lower endurance characteristics are observed in the device with a large SA-STI depth than in the device with a small SA-STI depth. The mechanisms underlying such unfavorable results are discussed on the basis of experimental data and technology computer-aided design simulations.

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Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Cited by 9 publications

References 35 publications

Charge Trapping and Reliability Properties of MONOS Memory with High-k Blocking Layer

Charge Trapping and Reliability Properties of MONOS Memory with High-k Blocking Layer

Investigation of Endurance Degradation in a CTF NOR Array Using Charge Pumping Methods

Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths

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