Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes

Wu, Yu-Ze; Chao, Mango C.-T.

doi:10.1109/vts.2008.16

Cited by 17 publications

(4 citation statements)

References 15 publications

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“…Most of the previous approaches are aimed at average power reduction, however they have also achieved some reduction in peak power as a by-product [1,11,9,16,14,17]. The approach by Chou et al [1] proposed the scheduling of test under power constraint, address power at module level, and not at circuit level.…”

Section: Previous Workmentioning

confidence: 99%

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Graph theoretic approach for scan cell reordering to minimize peak shift power

Tudu

Larsson

Singh

et al. 2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

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Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool.

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Section: Previous Workmentioning

confidence: 99%

“…Furthermore the proposal by Girard [14] also provides a power-area tradeoff. Wu et al [17] proposed a graph theoretic formulation of scan cells reordering for average power reduction. In this work, the Xs are preserved during the time of scan cells reordering for further optimization using MT-fill.…”

Section: Previous Workmentioning

confidence: 99%

Graph theoretic approach for scan cell reordering to minimize peak shift power

Tudu

Larsson

Singh

et al. 2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

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show abstract

“…Scan chain ordering, scan chain disabling techniques, and low-transition pattern generators were proposed to reduce excessive switching activity during testing. The scan chain ordering schemes [27]- [30] are an alternative to reduce switching activity by selecting scan cells with high internal switching power and reordering them to a location with low switching weights. However, these schemes can induce excessive routing overhead based on constraints on the position of scan cells.…”

Section: Introductionmentioning

confidence: 99%

A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs

Lee

Park

et al. 2021

IEEE Access

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Scan-based logic built-in self-test (LBIST) is widely used for supporting the in-system test in automotive systems. Although this technology has the advantage of low-cost testing, it suffers from low fault coverage and high switching activity during the test. This can lead to many undetected defects, excessive heat dissipation, and IR drop, inducing catastrophic risks to functional safety. Therefore, improving these two key factors is crucial to alleviate reliability problems in the automotive domain. Most previous works have focused on controlling the enormous toggling level of random patterns; however, one of the main disadvantages of these approaches is low fault coverage. Unfortunately, additional hardware costs associated with memory elements or test points are required for detecting the remaining faults. We propose a novel LBIST scheme based on weight-aware scan grouping and scheduling (WGS) to overcome these difficulties. Since the required test time of each automotive product is limited, the proposed scheme freezes the test time and focuses on improving both aforementioned factors significantly. Our approach divides scan cells into two categories: the coverage-efficient scan group and power-efficient scan group, and then it conducts weightbased scan cell reordering. Biased random patterns are fed to enhance fault coverage for the first category. For the second category, scheduling and disabling are performed to reduce switching activity. Finally, physical-aware reordering based on an inverter is performed to reduce routing overhead. Experimental results demonstrate the feasibility of the WGS methodology on the ITC'99 and OpenRISC benchmark circuits.INDEX TERMS Design for testability, low-power testing, scan-based logic BIST, scan cell ordering, scan chain scheduling.

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“…The increasing average power and peak power will have an adverse impact on the reliability of circuits and cause chip malfunction. Many techniques, such as scan chains modification [13] and reorder [16], power-aware ATPG [14], and X-filling [15], have been proposed to reduce test power.…”

Section: Introductionmentioning

confidence: 99%

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power

Han

2010

IEICE Trans. Inf. & Syst.

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SUMMARYTest data volume and test power are two major concerns when testing modern large circuits. Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying a single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques to optimize this method: a flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy can decrease the number of groups which need to be encoded and improve test data compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 25.6% and peak weighted switching activity by 9.68% during scan shift compared to selective encoding.

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Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes

Cited by 17 publications

References 15 publications

Graph theoretic approach for scan cell reordering to minimize peak shift power

Graph theoretic approach for scan cell reordering to minimize peak shift power

A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power

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