Scan-path architecture for pseudorandom testing

Dervisoglu, Bulent I.

doi:10.1109/54.32420

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Pscan 101011111

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1991

1999

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Cited by 7 publications

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“…Further details of the SCR's pseudorandom test capabilities can be found in [8]. There is also a pathlength register (R12) and a 32-bit iteration counter register (R8 and R9) which is used to specify the number of pseudorandom test vectors to be applied.…”

Section: Pscan 10101111mentioning

confidence: 99%

Features of a Scan and Clock Resource chip for providing access to board-level test functions

Dervisoglu

1991

J Electron Test

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The architecture and some of the specific features of a Scan and Clock Resource (SCR) chip are described. This chip is currently being used in a high-end workstation product to provide access to the testability features of the individual chips and/or printed circuit boards. Using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) is emerging as a common strategy for designing testable digital systems. Based upon experience gained from such an application, controller features that are deemed useful are discussed.

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Section: Pscan 10101111mentioning

confidence: 99%