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This paper discusses some of the critical issues that may prevent IEEE P1500 from becoming an acceptable standard and offers some suggestions for their solution. In particular, the inadequacy of the proposed P1500 and the VSIA solutions in handling hierarchical implementations is addressed. Support for hierarchical implementations is seen as an essential feature in a test access methodology that is intended for use in System on a Chip (SoC) designs. The author is actively pursuing some of these solutions through the working groups.

An architecture for implementing scan technology for test and debug in a state-of-the-art workstation is described. Architectural features include controlling the scan and clock functions from a single resource which can also perform Linear Feedback Shift Register (LFSR) based pseudo-random testing and test-result compression via signature capture. Operations of the scan subsystem are controlled from a Service Processor which uses a Diagnostics Bus to communicate with individual Scan and Clock Resource units present on each system board. For debug purposes the Service Processor has been linked with a remote computer and software has been developed to display and/or modify system state variables (flip-flops), Analysis of scan overhead indicate that benefits in test and debug of the target system far outweigh the cost of implementing scan technology for the APOLLO DN 10000 workstation.

This paper proposes a framework to help designers understand how to integrate customized Design for Test features under the guidelines of the 1149.1 standard. The paper begins by discussing the reasoning behind some of the essential features of the IEEE 1149.

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