Scan vector compression/decompression using statistical coding

Jas, A.; Ghosh-Dastidar, J.; Touba, N.A.

doi:10.1109/vtest.1999.766654

Cited by 218 publications

(198 citation statements)

References 8 publications

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“…It uses careful ordering of the test set and formation of cyclical scan chains to achieve compression with run-length codes. A general technique for statistically encoding test vectors for full scan circuits using selective Huffman coding is presented in [14]. Chandra and Chakrabarty have proposed test vector compression techniques based on Golomb codes [3,4] and frequency directed run-length (FDR) codes [5].…”

Section: Related Workmentioning

confidence: 99%

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Jas¹,

Touba²,

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

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Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.

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Section: Related Workmentioning

confidence: 99%

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Jas¹,

Touba²,

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

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“…Test data reduction can be achieved by both test compaction [3][4][5][6][7] and compression [8][9][10][11][12][13][14]. Several test data compression techniques have been proposed in the literature.…”

Section: Introductionmentioning

confidence: 99%

Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression

Al-Abaji

9th International Conference on Electronics, Circuits and Systems

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“…TDC has been approached from a number of research directions. For example, methods which (i) exploit the sparseness of care bits in the test set have been proposed in [2,6,17], and methods which (ii) exploit the regularities within the test set have been proposed in [5,12,18,21].…”

Section: Introductionmentioning

confidence: 99%