SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning

Abstract

Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM's write energy and latency. However, since different applications may require different retention times, STT-RAM retention times must be critically explored to satisfy various applications' needs. This process can be challenging due to exploration overhead, and exacerbated by the fact that STT-RAM caches are emerging and are not readily available for design time exploration. This paper explores using known and easily obtainable statistics (e.g., SRAM statistics) to predict the appropriate STT-RAM retention times, in order to minimize exploration overhead. We propose an STT-RAM Cache Retention Time (SCART) model, which utilizes machine learning to enable design time or runtime prediction of right-provisioned STT-RAM retention times for latency or energy optimization. Experimental results show that, on average, SCART can reduce the latency and energy by 20.34% and 29.12%, respectively, compared to a homogeneous retention time while reducing the exploration overheads by 52.58% compared to prior work.

STT-RAM-Based Hierarchical in-Memory Computing

“…The traditional CPU does not have any PiC/PiM optimization but features a relaxed retention STT-RAM cache of 75µs at L1 and 10ms at L2. Many prior works have indicated several energy and area benefits of replacing SRAM caches with STT-RAMs in different memory levels of traditional CPU-based computing [7], [14], [32], [33]. Thus, using STT-RAM caches with the base CPU allows us to robustly evaluate the added benefits of PiC/PiM architecture using STT-RAMs.…”

“…They utilized a sampling-based algorithm to determine the most suitable retention times for different applications dynamically. Similarly, Gajaria et al [14] found that specializing retention times of STT-RAM caches to the application needs improved performance and energy savings by 20.34% and 29.12%, respectively. In our work, we explore how relaxed retention STT-RAM can improve the efficiency of PiC operations.…”

“…In comparison, a shorter retention time will result in premature expiry of data blocks, leading to high miss rates and data movement overheads. Prior works mapped the retention time to workloads' execution characteristics in traditional CPUbased processing [9], [14]. However, we empirically found that such a scheme is unnecessary for PiC.…”

“…The heterogeneous cache consists of a high-retention time STT-RAM region for CPU-based computing and a lower retention time for PiC computing. A lower retention time region can reduce the write overheads whereas a higher retention time will increase the write overheads but will have fewer cache misses due to cache blocks expiring [9], [14]. For CPU-based computing, the cache block lifetime is much longer than in PiC-based computing, since blocks must be held in the cache for much longer.…”

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey

“…These NVM technologies offer diverse solutions for nonvolatile data storage with various advantages and characteristics. For instance, STT-MRAM has smaller cell area compared to SRAM, maintaining low programming voltage, fast write/read speed, and long endurance, making it an attractive replacement for embedded memories in the last level-cache and main memories [15], [16], [17]. PCRAM and ReRAM offer low programming voltage and fast write/read speed, making them attractive as a replacement for existing technologies in resource-constrained memory systems.…”