SCGPSim: A fast SystemC simulator on GPUs

Transaction level models of systems-on-chip in SystemC are commonly used in the industry to provide an early simulation environment. The SystemC standard imposes coroutine semantics for the scheduling of simulated processes, to ensure determinism and reproducibility of simulations. However, because of this, sequential implementations have, for a long time, been the only option available, and still now the reference implementation is sequential. With the increasing size and complexity of models, and the multiplication of computation cores on recent machines, the parallelization of SystemC simulations is a major research concern. There have been several proposals for SystemC parallelization, but most of them are limited to cycle-accurate models. In this paper we focus on loosely timed models, which are commonly used in the industry. We present an industrial context and show that, unfortunately, most of the existing approaches for SystemC parallelization can fundamentally not apply in this context. We support this claim with a set of measurements performed on a platform used in production at STMicroelectronics. This paper surveys existing techniques, presents a visualization and profiling tool and identifies unsolved challenges in the parallelization of SystemC models at transaction level.

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“…This has been studied by [4,24,25]. In [4,25] the authors have chosen to use CUDA (Compute Unified Device Architecture).…”

Section: Parallelization Inside Cyclesmentioning

confidence: 99%

“…An approach chosen in [2][3][4] is to run multiple processes concurrently inside a delta cycle, with a synchronization barrier at the end of each one. Parallel discrete event simulation (PDES) has been exploited, first, with a conservative approach [5][6][7][8], where all the time constraints are strictly fulfilled.…”

Section: Introductionmentioning

confidence: 99%

Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

2016

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“…In contrast to our work, this approach mainly relies on data-parallelism within complex events and does not explicitly attempt to achieve a high degree of task-parallelism between events. SCGPSim [17] is a simulation framework focusing on SystemC simulations. Using source-to-source compilation of SystemC to CUDA-enabled code, it automatically maps sequentially executing SystemC threads to parallel threads on a GPU.…”

Section: A Integrating Gpus With Pdesmentioning

confidence: 99%

Multi-level Parallelism for Time- and Cost-Efficient Parallel Discrete Event Simulation on GPUs

Kunz

Schemmel

Gross

et al. 2012

2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation

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Abstract-Developing complex technical systems requires a systematic exploration of the given design space in order to identify optimal system configurations. However, studying the effects and interactions of even a small number of system parameters often requires an extensive number of simulation runs. This in turn results in excessive runtime demands which severely hamper thorough design space explorations.In this paper, we present a parallel discrete event simulation scheme that enables cost-and time-efficient execution of large scale parameter studies on GPUs. In order to efficiently accommodate the stream-processing paradigm of GPUs, our parallelization scheme exploits two orthogonal levels of parallelism: External parallelism among the inherently independent simulations of a parameter study and internal parallelism among independent events within each individual simulation of a parameter study. Specifically, we design an event aggregation strategy based on external parallelism that generates workloads suitable for GPUs. In addition, we define a pipelined event execution mechanism based on internal parallelism to hide the transfer latencies between host-and GPU-memory. We analyze the performance characteristics of our parallelization scheme by means of a prototype implementation and show a 25-fold performance improvement over purely CPU-based execution.

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“…Specialized hardware including Field-Programmable Gate Array (FPGA) [4] and Graphics Processing Units (GPU) [5] can also boost simulation speed. The methodology presented in [6] parallelizes SystemC simulation across multicore CPUs and GPUs but the model needs to be partitioned on the heterogeneous simulator units.…”

Section: Related Workmentioning

confidence: 99%

Advances in Parallel Discrete Event Simulation for Electronic System-Level Design

et al. 2013

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SCGPSim: A fast SystemC simulator on GPUs

Abstract: SystemC promises an environment for faster hardware/ software design-space exploration.

Cited by 41 publications

References 6 publications

Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

Multi-level Parallelism for Time- and Cost-Efficient Parallel Discrete Event Simulation on GPUs

Advances in Parallel Discrete Event Simulation for Electronic System-Level Design

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