Schedulability and end-to-end latency in distributed ECU networks

Rajeev, A. C.; Mohalik, Swarup Kumar; Dixit, Manoj G.; Chokshi, Devesh B.; Ramesh, S.

doi:10.1145/1879021.1879039

Cited by 33 publications

(17 citation statements)

References 22 publications

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“…The focus here is on the FILO latency [11], which is the worst-case latency of the controller after a value change. A formal model for end-to-end paths is introduced in [3]. In this model, a system run r produces several timed paths (TPs) δ with timed events (k i ) and timestamps (e i ): δ = k 1 , e 1 , .…”

Section: Data-flow and Latency Semanticsmentioning

confidence: 99%

“…Knowing f p min makes it possible to exactly calculate the latency of the FILO pathP i,j , because this specifies the concrete finish time of a task instance (constraint II.1). This is done analogous to [3,11], whereas the transformation with TIC is respected. That means produced data elements are not available for the receiver task before the end of the producer period, if TIC is used.…”

Section: Parcusmentioning

confidence: 99%

“…An application has an acceptable first-in-last-out (FILO) latency [3], which is the maximum time between an input value change and its last corresponding controller output, for which the it is successfully validated and tested [4]. For example the time between the push on a gas pedal and the resulting injection.…”

Section: Introductionmentioning

confidence: 99%

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Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications

Kehr

Quiñones

Langen

et al. 2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Abstract-Embedded multicore processors are an attractive alternative to sophisticated single-core processors for the use in automobile electronic control units (ECUs), due to their expected higher performance and energy efficiency. Parallelization approaches for AUTOSAR legacy software exploit these benefits. Nevertheless, these approaches focus on extracting performance neglecting the system's worst-case sensor/actuator latency and energy consumption. This paper presents Parcus; an energy-and latency-aware parallelization technique that combines both runnable-and tasklevel parallelism. Parcus explicitly models the traversal of data from sensor to actuator through task instances, enabling to consider the latency imposed by parallelization techniques. The parallel schedule quality (PSQ) metric quantifies the success of the parallelization, for which it takes the latency and the processor frequency into account.We demonstrate the applicability of Parcus with an automotive case study. The results show that Parcus can fully utilize the processor's energy-saving potential.

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Section: Data-flow and Latency Semanticsmentioning

confidence: 99%

Section: Parcusmentioning

confidence: 99%

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Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications

Kehr

Quiñones

Langen

et al. 2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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“…They emphasized on the importance of two end-to-end latencies, i.e., "maximum age of data" and "first reaction" in control systems and body electronics domains respectively. A scalable technique for the computation of end-to-end latencies based on model checking is described in [17]. In this work, we will consider the analysis discussed in [16].…”

Section: B End-to-end Latency Analysismentioning

confidence: 99%

“…Hence, it is also important to compute the end-to-end latencies (or delays) in such systems. The end-to-end latency refers to the time elapsed between the arrival of a signal at the first task and production of actuation signal (in response to the input signal) by the last task in a data chain [17].…”

Section: A Problem Statementmentioning

confidence: 99%

Translating end-to-end timing requirements to timing analysis model in component-based distributed real-time systems

2012

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This is an accepted version of a paper published in ACM SIGBED Review. This paper has been peer-reviewed but does not include the final publisher proof-corrections or journal pagination.Citation for the published paper: Mubeen, S., Mäki-Turja, J., Sjödin, M. Abstract-Often, component-based real-time systems are modeled with trigger and data chains. The end-to-end timing requirements on trigger chains are different from those on data chains. For a trigger chain, the interest lies in the calculation of holistic response time and its comparison with end-to-end deadline. Whereas, the schedulability of a data chain requires a comparison between its end-to-end latencies and corresponding deadlines. We discuss the problem of translating end-to-end timing requirements unambiguously from component-based real-time systems into timing analysis models which are required as input by the analysis tools. We also provide preliminary guidelines for such translations in the existing industrial tool suite.

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Strukturierte Softwareentwicklung

Wolf

2023

Software Im Automobil

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Schedulability and end-to-end latency in distributed ECU networks

Cited by 33 publications

References 22 publications

Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications

Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications

Translating end-to-end timing requirements to timing analysis model in component-based distributed real-time systems

Strukturierte Softwareentwicklung

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